Location method for defect points of integrated circuit

Abstract

The invention belongs to the field of failure analysis for integrated circuits. The invention provides a location method for defect points of an integrated circuit. The method disclsoed by the invention comprises the following steps of: unsealing an integrated circuit, electrifying at both ends of a short-circuit pin of the integrated circuit to form a hot spot simultaneously, and then shooting via an infrared thermal imaging microscope, and comparing with a picture shot when the electrifying is not performed, and thus accurately locating an accurate position of a micro short circuit, and providing effective information for the follow-up further analysis. The location method for the defect points of the integrated circuit, disclosed by the invention, has the following advantages that 1. the method disclosed by the invention can accurately locate the defect points of a micro short circuit of the integrated circuit with fast speed, low cost and high efficiency; 2. the method disclosed by the invention has no injury on human bodies; and 3. the method disclosed by the invention greatly improves the success rate of packaging-level failure analysis.

Description

technical field [0001] The invention relates to a method for locating defect points of integrated circuits, in particular to a method for locating micro-short-circuit defects of integrated circuits. Background technique [0002] Wafer refers to the silicon wafer used in the production of silicon semiconductor integrated circuits. Because of its circular shape, it is called a wafer. Various circuit element structures can be processed on the silicon wafer to become IC products with specific functions. Chips made from wafers through complex manufacturing processes often cannot be directly soldered on circuit boards and powered on. Instead, they are packaged through packaging processes to achieve isolation from the external adverse environment and at the same time be connected to the circuit. The purpose of connecting the boards. At present, there are many packaging methods, such as QFP, DIP, TO220, SOP8, etc. These packages must use organic packaging materials and metal lead f...

AI Technical Summary

Problems solved by technology

[0005] In order to solve the problems in the prior art that the micro-short circuit defect point of the integrated circuit cannot be located, the defe...