Very long instruction word variable long instruction realization method and processor for realizing same

Abstract

The invention relates to a very long instruction word variable long instruction realization method and a processor for realizing the very long instruction word variable long instruction realization method. The method comprises the steps of: firstly splitting complicated computing operations which are difficultly realized by using instruction codes with fixed length or limited length into a plurality of simple instructions, issuing the plurality of simple instructions which have mutual data independence relationship into a plurality of hardware execution units of the processor in a single clock period, and concurrently completing complicated computing operations through data interaction and cooperation of the plurality of hardware execution units. The processor adopts multi-transmission technology, and data interaction behavior exists among the plurality of independent hardware execution units. According to the realization method and the processor provided by the invention, data interaction capability is increased among the plurality of execution units, and the plurality of instructions can be concurrently issued into the plurality of execution units, so that the execution efficiency can be improved; limit on the length of instruction codes can be broken through, and the plurality of instructions are concurrently executed in the same one clock period to realize complicated computing operations, so that the space of the instruction codes is expanded, and the data processing capability of the processor is enhanced.

Description

technical field [0001] The invention belongs to the field of instruction encoding architecture, and relates to the splitting of complex computing operation instruction encoding, in particular to a method for realizing super-long instruction words and variable-length instructions and a processor for realizing the method. Background technique [0002] For processor architectures that use fixed-length or finite-length instruction encoding, some complex calculation operations cannot be implemented with one instruction due to the limitation of the instruction encoding length. These complex calculation operations must be split into multiple data-dependent simple instructions. [0003] Classified according to the instruction set architecture, the processor architecture can be divided into two types: complex instruction set computing (CISC, Complex Instruction Set Computing) and reduced instruction set computing (RISC, Reduced Instruction Set Computing). [0004] In CISC architectu...

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Problems solved by technology

[0008] In order to overcome the deficiencies of the above-mentioned prior art, the purpose of the present invention is to provide a method for implementing super-long instruction word variable-length instructions and a processor for implementing the method, which solves the problem that complex calculation operations are difficult to implement with a single instruction

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