Test system and test method for memory
A test system and test method technology, applied in static memory, digital memory information, information storage and other directions, can solve the problems of complex method, test takes a lot of time, users can not understand the operation of the known test system, etc., to extend the scope of application. Effect
Inactive Publication Date: 2012-09-19
NAN YA TECH
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Problems solved by technology
However, the user cannot understand the operation of the known test system, nor can it detect errors of the known test system
[0003] In addition, because different system platforms have different methods of generating addresses, these methods cannot be applied to different system platforms or test machines
In addition, the known methods for generating addresses are complicated
Furthermore, testing within the system platform takes a lot of time
Method used
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Embodiment Construction
[0019] figure 1 It is a schematic flowchart illustrating a testing method according to an embodiment of the present invention. figure 2 A block diagram illustrating a test system according to an embodiment of the present invention. The testing system and testing method of the present invention can be used for testing memory, such as dynamic random access memory (DRAM). refer to figure 1 and figure 2 , The test system 20 for memory of the present invention includes: a control device 21 , an address generation device 22 , a data disturbance device 23 and a comparison device 24 . The control device 21 is used for writing a first data into a memory, as shown in step S11. In an embodiment of the present invention, before writing the first data into the memory, the control device 21 can be used to determine the first data, as shown in step S10. For example, the first data can be #00 (hexadecimal) or #FF (hexadecimal).
[0020] The address generating device 22 is used for gen...
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The test system for memory includes a controlling device, an address generating device, a data disturbing device and a comparing device. The controlling device is used for writing a first data into a memory. The address generating device is used for generating a plurality of first addresses and a plurality of second addresses corresponding to the memory. The data disturbing device is used for disturbing the first data using the first addresses to obtain a second data, and disturbing the second data using the second addresses to obtain a third data. The comparing device is used to for comparing the third data and the first data. By using the invention, the address can be used to simulate the test environment, and the parameters related to the addresses can be programmable to apply to different type of the memory so as to extend the coverage for the testing memory.
Description
technical field [0001] The present invention relates to a test system and a test method, in particular, to a test system and a test method for memory. Background technique [0002] Known test systems for memories must generate one or more precise addresses of the memory before the data at the addresses can be tested. Generally speaking, a known testing system for memory includes a testing machine and a system platform. After the testing machine receives the address from the system platform, it extracts data according to the address to complete the test. However, the user cannot understand the operation of the known test system, and cannot detect errors of the known test system. [0003] In addition, because different system platforms have different methods of generating addresses, these methods cannot be applied to different system platforms or test machines. In addition, methods for generating addresses are known to be complicated. Furthermore, testing within the system...
Claims
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Login to View More IPC IPC(8): G11C29/20
CPCG11C11/401G11C29/18
Inventor 杨永庆
Owner NAN YA TECH