Semiconductor device and memory protection method

A semiconductor and memory technology, applied in memory systems, instruments, preventing unauthorized use of memory, etc., can solve the problem of not distinguishing between main storage devices and auxiliary storage devices, and achieve the effect of protecting information

Active Publication Date: 2016-02-03
키오시아가부시키가이샤
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This is a memory management technology that manages storage devices as an address space without distinguishing between main storage devices and auxiliary storage devices

Method used

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  • Semiconductor device and memory protection method
  • Semiconductor device and memory protection method
  • Semiconductor device and memory protection method

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0030] A semiconductor device and a memory protection method will be described below according to a first embodiment.

[0031] 1. Setup of Semiconductor Devices

[0032] figure 1 is a block diagram of the semiconductor device according to this embodiment. Such as figure 1 As shown, the semiconductor device 1 includes a processor (MCU: Micro Control Unit) 10 , a memory device 20 , and MMUs (Memory Management Units) 30 and 31 .

[0033] The MCU 10 executes various types of processing using data held in the memory device 20 .

[0034] The storage device 20 includes a volatile semiconductor memory (eg, DRAM in this example) 21 and a nonvolatile semiconductor memory (eg, NAND flash memory in this example) 22 . The DRAM 21 is used as a cache memory of the NAND flash memory 22 . The storage device 20 holds various programs and data such as an OS (Operating System) and applications. DRAM 21 and NAND flash memory 22 are managed by single-level storage technology. Thus, the stora...

no. 2 example

[0106] A semiconductor device and a memory protection method according to a second embodiment are described below. The example at this time relates to the method of allowing worksets to refer to and add new data in the first embodiment. Since other configurations and operations are the same as in the first embodiment, description thereof will not be repeated.

[0107] 1. Data reference

[0108] First, the new data referencing method is described. Figure 15 It is a conceptual diagram of the virtual address space when viewed from workset WS1.

[0109] Such as Figure 15 As shown, the work set WS1 is a set of code CD1 and data D1 as described in the first embodiment. In pages PG45 to PG47 starting at virtual address ADD5, it is assumed that the memory device 20 stores data D3 not included in the work set WS1. The following assumes a situation in which workset WS1 requires data D3.

[0110] Figure 16 A flowchart showing the operation sequence of the semiconductor device 1...

no. 3 example

[0130] A semiconductor device and a memory protection method according to a third embodiment will be described below. This embodiment manages information in the storage device 20 using files and directories of the FAT (File Allocation Table) file system as in the first or second embodiment. Since other configurations and operations are the same as those in the first or second embodiment, description thereof will not be repeated.

[0131] 1. Using directory structure management

[0132] Figure 19 is a conceptual diagram of the virtual address space of the storage device 20 according to this embodiment. Assume that code CD1 is stored in pages PG0 to PG2, code CD2 is stored in pages PG10 to PG12, and data D1 is stored in pages PG30 to PG40, as Figure 19 shown.

[0133] In this case, the MCU 10 manages the code CD1 as a file AAA, manages the code CD2 as a file BBB, and manages the data D1 as two files CCC and DDD. In addition, MCU10 manages these files in a tree structure, ...

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PUM

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Abstract

The invention involves semiconductor devices and memory protection methods.Generally, according to an embodiment, a semiconductor device includes: processor; and storage device.The storage device has a non -easy -to -miss semiconductor memory and is configured as the main memory of the processor.When the processor executes multiple programs, the processor is used as a working set for each program to manage the information clips required by the program, and create a table for each working set.The relationship between the information fragment and the address of the information fragment in the storage device.The processor refers to the storage device for the corresponding table access for each work set.

Description

[0001] Cross References to Related Applications [0002] This application is based on and claims priority from prior Japanese Patent Application No. 2011-033719 filed on February 18, 2011, the entire contents of which are incorporated herein by reference. technical field [0003] Embodiments described herein relate generally to semiconductor devices and memory protection methods. Background technique [0004] Generally, a technique called a single-level memory structure is known. This is a memory management technology, which manages storage devices as an address space without distinguishing between main storage devices and auxiliary storage devices. [0005] In such a single-level storage technique, when a plurality of processes are executed, a technique of protecting information requested from one process to another process is important. Contents of the invention [0006] The invention provides a semiconductor device and a memory protection method capable of effectively...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/14
CPCG06F9/544G06F12/0246G06F9/524
Inventor 中井弘人金井达德前田贤一
Owner 키오시아가부시키가이샤
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