Composite type capacitor

A composite and capacitive technology, applied in circuits, electrical components, electric solid devices, etc., can solve the problems of high-frequency noise that is difficult to remove, and the increase of inductance in series with equal calibration, so as to achieve the effect of removing high-frequency interference

Active Publication Date: 2012-09-26
IND TECH RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In addition, with the acceleration of IC operating frequency, if the denoising at high frequency only depends on the decoupling capacitor on the circuit board, the transmission path will be too long under the IC multi-layer stack, resulting in an increase in the equivalent series inductance, high Frequency noise is not easy to remove

Method used

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  • Composite type capacitor
  • Composite type capacitor
  • Composite type capacitor

Examples

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Embodiment Construction

[0048] The invention will be more fully understood hereinafter with reference to the accompanying drawings, which show various embodiments of the invention. However, the invention may also be practiced in many different forms and should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and thereby fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of the various layers may be exaggerated for the sake of clarity.

[0049] figure 1 It is a substrate or a silicon interposer with a composite capacitor according to the first embodiment of the present invention. figure 2 yes figure 1 The schematic cross-section of the II-II line segment.

[0050] Please refer to figure 1 and figure 2 The composite capacitor 10 of the first embodiment includes a substrate 100 , at least one parallel-plate capacitor 110 and a...

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Abstract

The invention discloses a composite type capacitor comprising a substrate, at least a parallel-plate capacitor and at least a through-hole capacitor. The substrate is provided with through holes, and the parallel-plate capacitor is positioned on the substrate and comprises a first conductor layer, two dielectric layers and a second conductor layer. The at least one through-hole capacitor is connected with the at least one parallel-plate capacitor in parallel. The through-hole capacitor at least comprises an anode layer electrically connected to one face of the substrate with the first conductor layer, a first dielectric layer, a first cathode layer and a second cathode layer electrically connected to the other face of the substrate with the second conductor layer, and single poles of the parallel-plate capacitor and the through-hole capacitor are pulled out of the surface of the substrate. The anode layer is positioned on the inner surface of at least one through hole, and the surface of the anode layer is a multihole structure. The first dielectric layer is positioned on the multihole structure of the anode layer. The first cathode layer is covered on the surface of the first dielectric layer, and the second cathode layer is covered on the surface of the first cathode layer.

Description

[0001] This application is a divisional application of the invention patent application with the application number 200710305451.6 and the invention title "composite capacitor". technical field [0002] The present invention relates to a hybrid capacitor, and in particular to a hybrid capacitor capable of stabilizing voltage and reducing noise at high frequencies and a manufacturing method thereof. Background technique [0003] In order to meet the multi-functional requirements of electronic products, it is a technical trend of System in Package (SiP) to package ICs with different functions in a three-dimensional stacked form into a multi-functional IC module. When different ICs are integrated in a three-dimensional stack, in order to solve the problem of mismatching pins of the upper and lower ICs, an interposer layer will be added to re-layout the signals of the upper and lower chips to make the upper and lower ICs match. As the number of stacking layers increases, it is n...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/00H01L27/01H01L29/92
Inventor 李明林蔡丽端刘淑芬吴邦豪郑丞良
Owner IND TECH RES INST
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