Full chip esd protection circuit

Abstract

The invention discloses a whole-chip electrostatic discharge (ESD) protection circuit, which comprises a plurality of input / output (I / O) units, a plurality of power supply units and N ESD trigger units. The I / O units and the power supply units are arranged at intervals and are connected through an ESD trigger bus. Each I / O unit comprises an I / O port ESD circuit. Each power supply unit comprises a power supply ESD circuit. The N ESD trigger units are respectively arranged at the corners of a chip and are connected with the I / O units and the power supply units through the ESD trigger bus. The whole-chip ESD protection circuit has the advantages that since the ESD trigger units are placed at the corners of the chip, the area of the chip is not wasted, and the problem that ESD voltage of I / O links is mistakenly increased due to introduction of certain ESD voltage drop into a long discharge path in the prior art is solved at the same time.

Description

technical field [0001] The invention relates to an ESD protection circuit, in particular to a full-chip ESD protection circuit. Background technique [0002] Integrated circuit (IC) chips, with the evolution of manufacturing, the size of components has been reduced to the deep sub-micron stage, in order to improve the performance and operation speed of integrated circuits and reduce the manufacturing cost of each chip. However, with the shrinking of the component size, some reliability problems appear, such as electrostatic discharge (Electrostatic Discharge, ESD). Therefore, ESD protection circuits are often required. For full-chip ESD protection, the IO port ESD protection circuit and the ESD circuit of the power supply are essential. [0003] The traditional IO (input and output) port ESD protection circuit is usually divided into positive voltage protection circuit and negative voltage protection circuit, such as figure 1 As shown, the negative terminal of the positive...

AI Technical Summary

Problems solved by technology

However, the above-mentioned full-chip ESD protection has the following problems: 1. Each power supply ESD circuit needs an ESD trigger circuit, which is a waste of chip area; The long discharge path introduces a certain ESD voltage drop, which increases the ESD voltage of the IO link by mistake; 3. It is not easy to obtain a high-level ESD level when there are many chip pins; 4. In It is not easy to obtain a high level of ESD level in the case of multiple power supplies

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