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Multicore processor system

一种多核处理器、中央处理器的技术，应用在电数字数据处理、仪器、多道程序装置等方向，能够解决不能满足核间消息交互及任务调度等问题，达到提高效率和性能的效果

Active Publication Date: 2012-10-03
HUAWEI TECH CO LTD
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  • Abstract
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AI Technical Summary

Problems solved by technology

[0005] An efficient inter-core communication mechanism is an important guarantee for CMP's high performance; however, the existing CMP inter-core hardware message queue structure cannot meet higher performance inter-core message interaction and task scheduling

Method used

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  • Multicore processor system

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Embodiment Construction

[0015] One embodiment of the present invention provides a multi-core processor system. The system includes:

[0016] A plurality of central processing units and multiple sets of first-level hardware message queues; each central processing unit is respectively connected to a set of first-level hardware message queues for processing messages in the first-level hardware message queues; wherein, each A group of first-level hardware message queues includes multiple first-level hardware message queues; and, in each group of first-level hardware message queues, the first-level hardware message queues with higher priority are scheduled first, and the first-level hardware message queues with the same priority Level hardware message queues are scheduled round-robin according to the round-robin scheduling weight.

[0017] Another embodiment of the present invention also provides a multi-core processor system. The system includes:

[0018] Multiple central processing units, multiple se...

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Abstract

Provided is a multicore processor system comprising a plurality of central processing units and a plurality of level-one hardware message queue groups. Each central processing unit is separately connected to a level-one hardware message queue group and is used to process the messages of said level-one hardware message queues; each level-one hardware message queue group comprises a plurality of level-one hardware message queues; within each level-one hardware message queue group, level-one hardware message queues having highest priority are scheduled with priority, and level-one hardware message queues having identical priority are scheduled in a round-robin rotation according to round-robin scheduling weights. The multicore processor system of the present invention enhances the efficiency and performance of multicore processor systems.

Description

technical field [0001] The invention relates to the technical field of processors, in particular to a multi-core processor system. Background technique [0002] A single-chip multi-core processor (Chip Multi Processors, CMP for short) implements multiple processor units (Central Processor Unit, CPU for short) in one chip, and each CPU may also be called a core. The cores in the CMP share certain resources and can execute different processes in parallel. The programs executed by each core of the CMP sometimes need data sharing and synchronization, so the hardware structure of the CMP must support the communication between the cores. Currently, there are two mainstream inter-core communication mechanisms, one is a bus-shared cache memory (Cache) structure, and the other is a hardware message queue structure. [0003] The bus-shared Cache structure means that each core has a shared second-level or third-level Cache, which is used to store more commonly used data, and the data...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/50
CPCG06F9/544G06F9/546G06F2209/548
Inventor 张卫国邬力波
Owner HUAWEI TECH CO LTD
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