Multicore processor system

Abstract

Provided is a multicore processor system comprising a plurality of central processing units and a plurality of level-one hardware message queue groups. Each central processing unit is separately connected to a level-one hardware message queue group and is used to process the messages of said level-one hardware message queues; each level-one hardware message queue group comprises a plurality of level-one hardware message queues; within each level-one hardware message queue group, level-one hardware message queues having highest priority are scheduled with priority, and level-one hardware message queues having identical priority are scheduled in a round-robin rotation according to round-robin scheduling weights. The multicore processor system of the present invention enhances the efficiency and performance of multicore processor systems.

Description

technical field

[0001] The invention relates to the technical field of processors, in particular to a multi-core processor system. Background technique

[0002] A single-chip multi-core processor (Chip Multi Processors, CMP for short) implements multiple processor units (Central Processor Unit, CPU for short) in one chip, and each CPU may also be called a core. The cores in the CMP share certain resources and can execute different processes in parallel. The programs executed by each core of the CMP sometimes need data sharing and synchronization, so the hardware structure of the CMP must support the communication between the cores. Currently, there are two mainstream inter-core communication mechanisms, one is a bus-shared cache memory (Cache) structure, and the other is a hardware message queue structure.

[0003] The bus-shared Cache structure means that each core has a shared second-level or third-level Cache, which is used to store more commonly used data, and the data...

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