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Substrate stacking structure

A stacking structure and substrate technology, applied in the field of stacking structures, can solve problems such as broken metal wires, difficulty in reducing the thickness of the stacking structure, and difficult independent testing of chips on different platforms, etc., to achieve the effect of reducing the overall thickness

Inactive Publication Date: 2012-10-24
UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The technical problem to be solved by the present invention is to overcome the defects in the prior art that the thickness of the stacked structure is not easy to reduce, and the chips in the upper structure are not easy to be independently tested on different platforms, and the metal wires are easy to break, etc., to provide a Substrate stacking structure, which embeds chips in different substrates to reduce the overall thickness, and allows the chips in the substrate to be independently tested on different platforms

Method used

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Examples

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Embodiment Construction

[0056] see figure 2 with image 3 , which is a preferred embodiment of the present invention, where figure 2 It is a schematic diagram of the present invention, image 3 for figure 2 magnified schematic diagram.

[0057] refer to figure 2 , which is a substrate stack structure, including a first substrate (substrate) 1 embedded with a first chip (die) 11, a second substrate (substrate) 2 embedded with a second chip (die) 12, several connections to the above-mentioned The soldering part 3 of the first substrate 1 and the second substrate 2 , and a third die 4 disposed between the first substrate 1 and the second substrate 2 . Wherein, the above-mentioned soldering part 3 conducts the first substrate 1 and the second substrate 2 , and the first substrate 1 , the second substrate 2 and the soldering part 3 surround and form an accommodating space 5 . The third chip 4 is disposed in the accommodating space 5 and bonded to one end surface of the first substrate 1 , and th...

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Abstract

The invention discloses a substrate stacking structure which comprises a first substrate buried with a first wafer, a second substrate buried with a second wafer, a plurality of welded pieces and a third wafer. The welded pieces are connected between the first substrate and the second substrate and conduct the first substrate and the second substrate. An accommodation space is formed by the surrounding of the first substrate, the second substrate and the welded pieces. The third wafer is arranged in the accommodation space and jointed with the end face of the first substrate, and the third wafer is in electrical connection with the first wafer and the second wafer through the first substrate. Therefore, the overall thickness of the structure can be reduced, and the first wafer buried in the first substrate and the second wafer buried in the second substrate can be tested respectively and independently.

Description

technical field [0001] The present invention relates to a stacking structure, in particular to a substrate stacking structure. Background technique [0002] With the rapid development of electronic products, integrated circuits have become an indispensable product in the information age, such as notebook computers, mobile phones, personal digital assistants, and digital cameras, etc., and traces of integrated circuits can be seen everywhere. [0003] As far as the chip package in electronic products is concerned, in order to meet the needs of multi-function and high-speed and high-frequency computing of electronic products, it is necessary to increase the number of active components, but at the same time must meet the design requirements of light, thin, short, and miniaturized size. . [0004] In response to the demand for accommodating a large number of electronic components in a limited construction space, there are currently many integrated circuit packaging types availa...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/00H01L25/18H01L23/31
CPCH01L25/105H01L2224/04105H01L2224/16227H01L2224/32145H01L2224/32225H01L2224/48091H01L2224/48227H01L2224/73204H01L2224/73265H01L2225/1023H01L2225/1035H01L2225/1058H01L2924/15331H01L2224/19H01L2224/20H01L2924/00012H01L2224/16225H01L2924/00
Inventor 刘祐成陈建男
Owner UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO LTD
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