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Delay phase-locked loop

A delay-locked loop, delay time technology, applied in the direction of electrical components, automatic power control, etc., can solve problems such as unbearable use and errors

Active Publication Date: 2014-09-17
FARADAY TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

like image 3 As shown, the output clock signal CKOUT-2 is wrongly locked at 2T. Due to the fixed proportional relationship of the delay time, the corresponding five-phase clock signal PHS-2 is wrong and unusable.

Method used

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Examples

Experimental program
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Embodiment Construction

[0036] Figure 4 is a schematic diagram of a delay locked loop 400 according to an embodiment of the present invention. The delay locked loop 400 receives a reference clock signal FREF and outputs a clock signal CKOUT. The delay locked loop 400 includes a phase detector 410 , a delay chain 430 , a false lock prevention circuit 440 , and a loop filter 420 . The phase detector 410 outputs the comparison signal CMP1 according to the phase comparison between the reference clock signal FREF and the output clock signal CKOUT. The delay chain 430 delays the reference clock signal FREF by different times to generate a plurality of phase clock signals PHS and output clock signals CKOUT, wherein the delay time of each phase clock signal PHS and the output clock signal CKOUT have a preset ratio. The false lock prevention circuit 440 outputs the comparison signal CMP2 according to the phase comparison between the reference clock signal FREF and the aforementioned plurality of phase cloc...

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Abstract

A delay locked loop receives a reference clock signal and outputs an output clock signal. The delay locked loop includes a phase detector, a delay chain, a false lock prevention circuit and a loop filter. The phase detector outputs a first comparison signal based on phase comparison between the reference clock signal and the output clock signal. The delay chain delays the reference clock signal at different times to generate multiple phase clock signals and an output clock signal. The false lock prevention circuit outputs a second comparison signal based on phase comparison between the reference clock signal and the plurality of phase clock signals. The loop filter controls the delay time of the output clock signal according to the first comparison signal and the second comparison signal, so that the delay time of the output clock signal is equal to a preset value.

Description

technical field [0001] The present invention relates to a delay-locked loop (DLL for short), and more particularly to a delay-locked loop capable of preventing false lock. Background technique [0002] figure 1 is a schematic diagram of a known delay locked loop 100 . The delay locked loop 100 receives an external reference clock signal FREF and outputs a clock signal CKOUT for use by internal circuits. The delay locked loop 100 includes a phase detector 110 , a loop filter 120 , and a delay chain 130 . The phase detector 110 outputs a comparison signal CMP according to a phase comparison of the reference clock signal FREF and the output clock signal CKOUT. The delay chain 130 delays the reference clock signal FREF to generate the output clock signal CKOUT. The loop filter 120 is a low-pass filter, which can filter the noise of the comparison signal CMP, and also control the delay time of the delay chain 130 for the output clock signal CKOUT according to the comparison s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/06
Inventor 林志宪穆志伟余明士
Owner FARADAY TECH CORP