IP core detection layout, layout design system and layout design method

Abstract

The invention provides an IP (Internet Protocol) core detecting layout, a layout design system and a layout design method. The IP core detecting layout comprises an IP core layout; the layout at the middle part of the IP core layout is removed, only the layouts in the edge areas of the IP core layout are kept, therefore, the IP core detecting layout is annular, moreover, the space between the edge of an internal ring of the IP core detecting layout and the edge of an external ring of the IP core detecting layout is not less than the maximum space between current different circuit structures based on the design principle. The IP core detecting layout and ambient circuit layouts are combined to carry out detection based on the design principle; if conflict between the IP core detecting layout and the ambient circuit layouts exists, the ambient circuit layouts can be modified immediately, therefore, the design time of a system on chip can be saved; moreover, an IP core user just can obtain the layout of the edge areas instead of the circuit or the layout of the whole IP core through the IP core detecting layout, so that benefit is provided for protecting the intellectual property of the IP core.

Description

technical field [0001] The invention relates to the design of an on-chip system, in particular to an IP core detection layout for design rule detection, a layout design system and a layout design method for performing on-chip system layout design using the IP core detection layout. Background technique [0002] With the rapid development of ultra-large-scale integrated circuits, the integration of semiconductor chips is increasing, which allows the functions previously implemented by multiple chips to be integrated into a single chip, thus forming a powerful system on chip (System on Chip, SOC). ). [0003] Due to the complex structure of the system on a chip, it will cost a lot of manpower and material resources if it is designed from scratch every time. In addition, due to the ever-shortening life cycle of electronic products, chip design is also required to be completed in a shorter time. In order to speed up the design speed of the system on a chip, people package the ...

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Problems solved by technology

Moreover, the hard core provider is generally a chip manufacturer. When providing the IP core to various IP core users, in order to protect the intellectual property rights of its own IP core, it will not inform the specific circuit and layout of the IP core. The IP core user only informs the IP core user of the size, size, port, type, parameter and location of the IP core connected to the surrounding circuit, and the IP core user uses the information to design the circuit around the IP core and the corresponding surrounding circuit. Circuit layout, but this will cause a lot of trouble for IP core users when designing the surrounding circuit layout

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