Clock protection method and device

Abstract

Disclosed are a clock protection method and device. The method comprises: determining an active / standby state of a current board; when the board is a standby board, determining whether a phase locked loop of the board is locked; when the phase locked loop of the board is unlocked, determining whether an unlocking time exceeds a preset threshold; when the unlocking time does not exceed the preset threshold, determining whether a phase locked loop of an active board is locked, and if the phase locked loop of the active board is unlocked, switching the standby board into an active board and clearing the unlocking time. The technical solution provided by the present invention solves the problem in the prior art that it is difficult to determine, only according to a running state of the phase locked loop, whether the clock needs to be switched and whether a new apparatus needs to be introduced for phase locked loop detection, avoids determining whether a fault point is a phase locked loop circuit or a clock source, and implements protection switching when the clock is asynchronous and the service is damaged without adding an external apparatus.

Description

technical field [0001] The present invention relates to the communication field, in particular to a clock protection method and device. Background technique [0002] For a synchronous communication system, it is very important to achieve clock synchronization between devices. Current devices usually use a 1+1 or 1:1 hot backup interlock clock scheme. Switch to the standby clock to ensure clock synchronization and reduce service damage. [0003] General equipment uses a phase-locked loop circuit to track and synchronize the external clock. However, the device aging rate of the first analog PLL or half-analog and half-digital PLL is relatively high, and failures often occur due to problems with PLL circuit components; second, whether the PLL circuit can achieve synchronization and simultaneously follow the lock The phase loop circuit is related to the clock source, and it is difficult to judge whether the clock needs to be switched simply from the operating state of the phas...

AI Technical Summary

Problems solved by technology

However, the device aging rate of the first analog PLL or half-analog and half-digital PLL is relatively high, and failures often occur due to problems with PLL circuit components; second, whether the PLL circuit can achieve synchronization and simultaneously follow the lock The phase loop circuit is related to the clock source, and it is difficult to judge whether the clock needs to be switched simply from the operating state of the phase-locked loop; third, for the performance detection of the phase-locked loop circuit device, it is generally necessary to introduce a new detection circuit, which increases the cost and cost of the equipment. new failure point

To address these problems, no effective solutions have been proposed

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