On-chip communication method and device of integrated circuit based on asynchronous structure

Abstract

The invention discloses an on-chip communication method and an on-chip communication device of an integrated circuit based on an asynchronous structure. The structure comprises the following steps of 1, directly connecting main equipment to each auxiliary equipment request interface by a request bus in advance, sequentially and serially connecting a plurality of auxiliary equipment response interfaces to form an auxiliary equipment response chain in advance, and connecting the auxiliary equipment response interface on the head of the auxiliary equipment response chain with a main equipment response interface; and 2, when the main equipment communicates with the auxiliary equipment, receiving a request message consisting of a plurality of micro-packets from the main equipment by the auxiliary equipment through the request bus, and sending a response message consisting of the micro-packets to the main equipment by the auxiliary equipment through the auxiliary equipment response chain. The device comprises the main equipment and the auxiliary equipment, wherein the main equipment is directly connected with each auxiliary equipment through the request bus, the auxiliary equipment are sequentially and serially connected to form the auxiliary equipment response chain, and the auxiliary equipment on the head of the auxiliary equipment response chain is connected with the main equipment. The method and the device have the advantages that the number of long signal lines is little, the occupation of hardware resources is little, and the expandability is good.

Description

technical field [0001] The invention relates to the field of on-chip communication of an integrated circuit SOC chip, in particular to a method and device for on-chip communication of an integrated circuit based on an asynchronous structure. Background technique [0002] With the rapid increase in the scale and design complexity of integrated circuit SOC chips, the research on the SOC on-chip bus structure has attracted more and more attention, and a variety of on-chip buses have been developed, such as AMBA, CoreConnect, etc. These buses are all synchronous bus types. It has the advantages of high bandwidth and low delay, but requires that the devices on the bus belong to the same clock domain, and the number of interconnection lines of this type of bus is large, which takes up more hardware resources. However, in integrated circuits, some components do not require high-speed access interfaces, but are more concerned about reducing the occupation of hardware resources and t...

AI Technical Summary

Problems solved by technology

[0005] (1) In the daisy chain DCR bus, when multi-level slave devices are cascaded with the master device, there will be a large number of long communication lines between the master and slave devices, occupying a large amount of wiring resources, increasing the chip area and the difficulty of physical implementation;

[0006] (2) The daisy chain DCR bus only supports read and write information transmission, and does not support other types of information transmission such as slave device interrupts

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