Cyclic floating-point number generator, cyclic floating-point number adder, method for generating cyclic floating-point numbers and method for adding cyclic floating-point numbers

Abstract

An aspect of the invention is to provide a cyclic floating point number generator (400) for generating a cyclic floating point number comprising a sign bit field (S), an exponent field (E) and a cyclic mantissa field (M) from an input fixed point number. The generator assigns the input bits in a fixed-point number to a plurality of slots, generates a sign bit field (S), generates an exponent field (E) based on the bit position of the leading significant bits, and extracts the first group of bits and the second bit group, and the mantissa field (M) is generated by providing the start bit of the first bit group after the last bit of the second bit group.

Description

technical field [0001] The present invention relates to a cyclic floating-point number generator and a cyclic floating-point number adder, in particular to a generator for generating a cyclic floating-point number from an input fixed-point number and a calculation unit for adding two cyclic floating-point numbers including a cyclic mantissa. Background technique [0002] In computer or arithmetic hardware, integers and floating-point numbers have been used extensively to simply describe extremely large or extremely small values. In the integer format, it is easy to make hardware perform calculations, however, there is a drawback that the integer format can represent a small range. Therefore, the algorithm must be scaled such that overflow does not occur. In floating-point format, a wide range of values ​​can be represented without conversion algorithms to prevent overflow. [0003] The IEEE-754 format is the most commonly used format for floating-point representation. fig...

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Problems solved by technology

[0011] Even with the type of floating-point adder shown above, its implementation is complex, and the size of the adder is several times larger than that of an integer adder, because the barrel shifter and subtractor require larger-sized logic circuits, This makes the critical path longer

In addition, the logic delay of the adder is also large, which results in a limited operating clock frequency and sometimes requires the preparation of additional pipeline stages that also require additional hardware size

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