A kind of soc integrated multi-port ddr2/3 scheduler and scheduling method

Abstract

The invention discloses an SoC (System on a Chip)-integrated multi-port DDR2 / 3 scheduler and a scheduling method. The scheduler adopts the structure that a scheduling IP (Intellectual Property) core is in series connection with the input terminal of a traditional scheduler, a state machine IP core is connected in series with the output terminal of the traditional scheduler, and the scheduling IP core comprises a port lookup table and an improved scheduler. The memory types of all ports in the table are looked up via a dynamic query port, the time-delay sensitive, bandwidth sensitive and deadline sensitive memory demands are scheduled according to corresponding scheduling strategies, then secondary command queuing is conducted by the traditional scheduler and the state machine IP core, and a command queue sent to a DRAM (Dynamic Random Access Memory) chip is finally generated. The method meets the requirements of LCD controllers and other deadline sensitive equipment, meanwhile, effectively shortens the average response time of time-delay sensitive equipment, improves the effective bandwidth utilization ratio of bandwidth sensitive equipment and finally promotes the QoS (Quality of Service) of the whole system.

Description

technical field [0001] The invention relates to a SoC integrated multi-port DDR2 / 3 scheduler and a scheduling method, belonging to the field of SoC storage. Background technique [0002] With the development of microelectronic technology, the embedded computing platform based on SoC (System-on-a-Chip) is becoming more and more mature. However, due to the ever-increasing gap between processor speed and external memory speed (also known as the "memory wall" problem), SoC memory systems have become a bottleneck for system performance, power consumption, and cost. Therefore, how to optimize the storage system, especially the architecture and management strategy of the memory controller, has always been a hot spot in the research of embedded SoC chips. [0003] In order to improve the overall performance of embedded systems, modern high-performance SoC chips generally use the following two different ways to support multiple concurrent access requests initiated by the memory cont...

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Problems solved by technology

[0007] Purpose of the invention: the present invention proposes a SoC-integrated multi-port DDR2 / 3 scheduler and a scheduling method, which solves the effective problem exposed when the multi-port DDR2 / 3 controller integrated in the existing SoC chip is accessed concurrently by different types of master devices. Low bandwidth utilization and poor QoS

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