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High-frequency clock duty-ratio test circuit

A technology of duty ratio and comparison circuit, which is applied in the direction of monitoring pulse chain mode, etc., and can solve the problems of reducing clock frequency, clock duty ratio test, interference, etc.

Inactive Publication Date: 2013-07-03
BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to prevent the distortion of the clock waveform and affect the accuracy of the test results, the duty ratio test has high requirements on the IO drive capability, but if the IO drive capability is too large, it will cause interference to other circuits under the same power system.
If the high-frequency clock uses digital frequency division to reduce the clock frequency, the clock duty cycle cannot be tested after frequency division

Method used

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  • High-frequency clock duty-ratio test circuit
  • High-frequency clock duty-ratio test circuit
  • High-frequency clock duty-ratio test circuit

Examples

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Embodiment Construction

[0016] The circuit implementation structure is specifically introduced below in conjunction with the accompanying drawings, such as image 3 shown. The waveform diagram of each node inside the circuit, such as Figure 4 shown.

[0017] The integral circuit is controlled by the counter inside the control logic, and integrates within N clock cycles. The integral unit is composed of a switched capacitor charge and discharge circuit and a source follower circuit. The source follower circuit makes the integral output voltage have a certain current drive capability to divide the voltage. Generate the reference voltage required by the comparison circuit. The control circuit outputs a signal CON representing the integration interval, and CON is used as an input of an integration unit to generate a reference voltage Vtotal. The AND of the integration interval signal CON and the clock signal CLK is used as an input of another integration unit to generate an evaluation voltage Veval. ...

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Abstract

The invention provides a high-frequency clock duty-ratio test circuit, which is characterized in that a switched capacitance structure is used for converting time values to voltage values, the high-low level time is amplified in equal proportion through the quantitative comparison of the voltage, so that the high test accuracy of the duty ratio of a high-frequency clock signal is realized. The test precision of the duty ratio does not depend on the realization technology and only depends on the design precision.

Description

Technical field: [0001] The invention relates to a test circuit for the duty ratio of a high-frequency clock, which uses a switched capacitor structure to convert the amount of time into a voltage amount, and amplifies the high and low level time of the clock in equal proportions through quantitative comparison of the voltage, so as to realize the performance of the duty ratio of the high-frequency clock The accurate test can be used for the clock double-edge working system test to evaluate the clock duty cycle. Background technique: [0002] On-chip clock generation circuits, such as phase-locked loops, frequency synthesizers, oscillators, etc., are widely used in various chips to provide clocks for digital circuit work and timing for data transmission of communication interfaces. In order to improve the working speed of the chip, some applications use clock double edge to work. In order to ensure the correctness of the timing, certain constraints are put forward on the du...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/19
Inventor 高慧
Owner BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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