System and method for extracting capacitance parameters of integrated circuits based on GPU

Abstract

The invention discloses a GPU(graphic processing unit)-based system and method for extracting a capacitance parameter of an integrated circuit. The system comprises a random walk start module, a random walk jump module and a random walk statistic module, wherein all modules achieve data exchange on a global memory of a GPU; each module operates a plurality of GPU threads in parallel; in the random walk start module, each GPU thread generates a specified number of walk starting points and acquires corresponding weights of the walk starting points; in the random walk jump module, each GPU thread performs specified times of random walks and acquires an identifier of a conductor hit during each walk; and in the random walk statistic module, each GPU thread reads the specified number of identifiers of the hit conductors and weights of corresponding walk starting points so as to calculate the accumulated capacitance value and the accumulated capacitance quadratic sum. If the relative error of the self-capacitance of a main conductor does not reach the target accuracy, the number of paths required to be covered is estimated. The system and the method can achieve rapid extraction for the capacitance parameter of the integrated circuit.

Description

Technical field [0001] The invention relates to the field of VLSI (Very Large Scale Integrated circuits) physical design, in particular to the extraction of integrated circuit interconnect capacitance parameters and circuit delay analysis. Background technique [0002] In the design process of integrated circuits, the function description is first proposed, and then the layout describing the semiconductor process size and structure is obtained through logic design and layout design. Finally, the layout verification is performed, that is, whether the above design meets the requirements through computer software simulation. If the requirements are met, proceed to the next step of manufacturing. Otherwise, if the requirements are not met, return to the logic design and layout design to make necessary corrections. In layout verification, an important link is "interconnect parasitic parameter extraction". [0003] With the development of integrated circuit manufacturing technology, ci...

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Problems solved by technology

However, the method for extracting capacitance parameters in said paper is still time-consuming, therefore, its efficiency needs to be improved

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