Integrated circuit device and method for performing conditional negation of data

Abstract

An integrated circuit device (105) comprises at least one digital signal processor (DSP) module (100), and the at least one DSP module (100) comprises a first data register and at least one further data register (140) and at least one data execution unit (DEU) module (120) arranged to execute operations on target data stored within the first data register and the at least one further data register (140). The at least one DEU module (120) is arranged, upon receipt of a conditional negation instruction (210), to retrieve at least one conditional bit value (225, 325) from the first data register (220), and conditionally perform negation of target data within the at least one further data register (230) according to the at least one retrieved conditional bit value (225, 325).

Description

technical field [0001] The field of the invention relates to integrated circuit devices and methods of implementing conditional negation of data stored in data registers of a data signal processor (DSP) device. Background technique [0002] Digital signal processor (DSP) applications are becoming more and more stringent in terms of requirements for the DSP core. For example, the increased data rates specific to the fourth generation (4G) of mobile communication systems require significantly higher DSP performance. One of the key operations performed by a DSP within such a 4G mobile communication system is descrambling of received bits. [0003] The scrambling operation performed on the data bits to be transmitted comprises performing a bit operation XOR (exclusive OR) between the data bits to be transmitted and a given sequence of scrambling bits. Upon subsequent reception of data, it is necessary to reverse the process by performing another bit XOR operation between the r...

AI Technical Summary

Problems solved by technology

Furthermore, with a limited number of available predicate bits, regardless of the processing parallelism capabilities within the DSP architecture, the use of "conditional" statements to enforce conditional negation of LLR values ​​may prevent more than one conditional negation operation per cycle from being implemented

Also, extracting the scrambled bit sequence required to perform the descrambling operation consumes DSP cycles

[0005] Since this conditional negation of LLR values ​​may be required to be performed on a regular basis within a mobile communication receiver, reducing the effectiveness of the DSP performing this operation can significantly affect the overall DSP performance

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