Data buffering method in multi-core processor

Abstract

The invention provides a data buffering method in a multi-core processor. The data buffering method in the multi-core processor comprises the steps of receiving a command for concurrently executing multiple threads; independently assigning each of the multiple threads to multiple cores of the processor respectively, wherein each of the multiple cores of the processor is assigned with one thread at most; responding to caching requests regarding each core, with the assigned thread, of the processor during the period that the threads are executed, and storing caching data to a coupled special buffer storage; when caching storages which are larger than or equal to a threshold value t in number store the same caching data, storing the same caching data to a general buffer storage. Through the data buffering method in the multi-core processer, the caching assess speed and the replacement speed are improved, and the problem of false sharing is overcome.

Description

Technical field

[0001] The present invention relates to the field of data storage, in particular to a method for buffering data in a multi-core processor, and further relates to a method for multi-level buffering of data in a multi-core processor. Background technique

[0002] The speed gap between the processor and main memory is a prominent contradiction for multi-core processors, so multi-level cache must be used to alleviate it. Currently, there are multi-core processors that share the first-level cache, multi-core processors that share the second-level cache, and multi-core processors that share the main memory. Generally, a multi-core processor adopts a multi-core processor structure that shares a second-level cache, that is, each processor core has a private first-level cache, and all the processor cores share the second-level cache. The architectural design of the cache itself is also directly related to the overall performance of the system. However, in the multi-core ...

Images