Data buffering method in multi-core processor

A multi-core processor and data buffering technology, which is applied in the direction of electrical digital data processing, instruments, memory systems, etc., can solve the problems of long hit time, high algorithm complexity, false sharing, etc., and achieve reduced hit time and low algorithm complexity , the effect of improving the overall efficiency

Active Publication Date: 2013-10-09
四川千行你我科技股份有限公司
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Problems solved by technology

[0007] In order to solve technical problems such as high algorithm complexity, long hit time, false sharing and other technical problems in the reading and replacement algorithms of the cache in the existing multi-core processor system, the present invention provides a method for buffering data in the multi-core processor

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  • Data buffering method in multi-core processor

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Embodiment Construction

[0026] figure 1 Shows the structure block diagram of the multi-core processor involved in the present invention, such as figure 1 As shown, the multi-core processor in the present invention includes a plurality of processor cores, a plurality of dedicated buffer memories that form a one-to-one coupling relationship with the plurality of processor cores, and a plurality of dedicated buffer memories respectively coupled to the plurality of processor cores. A general-purpose buffer memory, wherein the plurality of dedicated buffer memories are only used to store cache data related to threads executed by a processor core coupled with the plurality of dedicated buffer memories, and the one general-purpose buffer memory is used for storing and Cache data related to threads executed by each processor core. The multi-core processor also includes a mapping buffer for storing a cache mapping table. The cache mapping table stores at least the storage relationship between the cache data a...

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Abstract

The invention provides a data buffering method in a multi-core processor. The data buffering method in the multi-core processor comprises the steps of receiving a command for concurrently executing multiple threads; independently assigning each of the multiple threads to multiple cores of the processor respectively, wherein each of the multiple cores of the processor is assigned with one thread at most; responding to caching requests regarding each core, with the assigned thread, of the processor during the period that the threads are executed, and storing caching data to a coupled special buffer storage; when caching storages which are larger than or equal to a threshold value t in number store the same caching data, storing the same caching data to a general buffer storage. Through the data buffering method in the multi-core processer, the caching assess speed and the replacement speed are improved, and the problem of false sharing is overcome.

Description

Technical field [0001] The present invention relates to the field of data storage, in particular to a method for buffering data in a multi-core processor, and further relates to a method for multi-level buffering of data in a multi-core processor. Background technique [0002] The speed gap between the processor and main memory is a prominent contradiction for multi-core processors, so multi-level cache must be used to alleviate it. Currently, there are multi-core processors that share the first-level cache, multi-core processors that share the second-level cache, and multi-core processors that share the main memory. Generally, a multi-core processor adopts a multi-core processor structure that shares a second-level cache, that is, each processor core has a private first-level cache, and all the processor cores share the second-level cache. The architectural design of the cache itself is also directly related to the overall performance of the system. However, in the multi-core ...

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Application Information

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IPC IPC(8): G06F12/08G06F12/084
Inventor 毛力
Owner 四川千行你我科技股份有限公司
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