Multiple times programmable memory cell and method for forming same

Abstract

A device includes an active region and a coupling capacitor. The capacitor includes a first floating gate, an upper plate of the capacitor serving as a coupling capacitor, and a doped semiconductor region, a lower plate of the capacitor serving as a coupling capacitor. The doped semiconductor region includes a surface portion located at the surface of the active region, and a sidewall portion lower than the bottom surface of the surface portion. The sidewall portion is located on the sidewall of the active region. A capacitor insulator is disposed between the capacitor upper plate and the capacitor lower plate. The capacitor insulator includes an upper portion, and a sidewall portion lower than a bottom surface of the upper portion. The invention also provides the multi-time programmable storage unit and its forming method.

Description

technical field [0001] The present invention generally relates to the field of semiconductor technology, and more specifically, relates to multiple times programmable memory cells. Background technique [0002] A multiple-time programmable (Multiple-Time Programming, MTP) storage unit can retain information stored in the storage unit even if the power is cut off. Typically, to form an MTP memory cell, a standard complementary metal oxide semiconductor (CMOS) based logic process is used as a starting basis. Additional process steps may be incorporated into the logic process flow to form the MTP memory cell. Examples of such additional process steps include second polysilicon deposition, junction dopant optimization, and the like. MTP memory cells generally require larger capacitors to improve the programming efficiency of the MTP memory cells. Therefore, the chip area occupied by the MTP storage unit is large. Contents of the invention [0003] In order to solve the def...

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Problems solved by technology

Therefore, the chip area occupied by the MTP memory cell is larger

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