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Layout design with via routing structure

A technology of circuit structure and layer structure, which is applied in the direction of circuits, semiconductor/solid-state device components, semiconductor devices, etc.

Active Publication Date: 2013-11-13
GLOBALFOUNDRIES U S INC MALTA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, conventional techniques may require triple patterning to form diffused contacts and Metal 1 layer to meet top-to-top spacing requirements between diffused contacts (e.g. in power rail regions) and Metal 1 layer structures used for 14nm technology node and beyond structure

Method used

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  • Layout design with via routing structure
  • Layout design with via routing structure
  • Layout design with via routing structure

Examples

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Embodiment Construction

[0020] In the following, for purposes of explanation, specific details are presented so as to obscure the exemplary embodiments. It is understood, however, that the exemplary embodiments may be practiced without these specific details or with equivalent arrangements. In other instances, common structures and devices are presented in block diagram form in order to avoid unnecessarily obscuring the embodiments. In addition, unless otherwise specified, all numerical quantities, ratios, and attribute values ​​of ingredients, reaction conditions, and other numerical values ​​used in the specification and claims are modified by the word "approximately".

[0021] The present disclosure addresses and solves the problems of reduced wiring integrity (eg, caused by CA jumper configurations) and increased patterning costs associated with wiring design. The disclosure provides, inter alia, a via wiring structure over a portion of the diffusion contact and / or gate contact to couple the dif...

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Abstract

An approach for providing layout designs with via routing structures is disclosed. Embodiments include: providing a gate structure and a diffusion contact on a substrate; providing a gate contact on the gate structure; providing a metal routing structure that does not overlie a portion of the gate contact, the diffusion contact, or a combination thereof; and providing a via routing structure over the portion and under a part of the metal routing structure to couple the gate contact, the diffusion contact, or a combination thereof to the metal routing structure.

Description

technical field [0001] The present disclosure relates to wiring design. The present disclosure is particularly applicable to designs beyond the 14nm technology node. Background technique [0002] As technology advances, layout must also be designed to meet scaling requirements, for example, based on ever-decreasing technology node sizes, which may result in significant process integration risks for mid-line (MOL) processes. For example, in order to meet size scaling requirements, designers typically utilize configurations such as diffused junction crossovers (CA crossovers) to implement cross-coupling-based designs. However, as technology nodes continue to shrink, the use of CA jumpers increases the risk of accidental activation of transistors and other integrated structures, reducing overall device integration. Furthermore, due to the reduction of technology nodes, the cost related to masks (such as diffusion contacts, metal 1-layer structure, etc.) in the MOL process has...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L23/528
CPCH01L23/528H01L21/768H01L21/76895H01L2027/11875H01L27/0207H01L27/11807H01L2924/0002H01L2924/00
Inventor Y·马J·桂H·莱文森H·吉田M·拉希德
Owner GLOBALFOUNDRIES U S INC MALTA
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