Layout fast reading method

A layout-reading, fast technology, applied in the direction of instrumentation, computing, electrical digital data processing, etc., can solve problems such as increasing program memory consumption, affecting program operating efficiency, and unfavorable scalability of simulation software, so as to reduce memory usage and improve Flexibility and the effect of improving operational efficiency

Active Publication Date: 2013-12-04
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
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  • Application Information

AI Technical Summary

Problems solved by technology

These data structures and their index relationships will be accessed frequently in the subsequent layout division and feature extraction process, which not only affects the running efficiency of the program, but also increases the memory consumption of the program by establishing more data structures. As the capacity of the layout file is getting larger and larger, this method will no longer be applicable, and it will be quite unfavorable for the scalability of the simulation software

Method used

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Embodiment Construction

[0017] Embodiments of the invention are described in detail below, examples of which are illustrated in the accompanying drawings. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

[0018] The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Of course, they are only examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and / or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. Descriptions of well-known components and processing te...

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Abstract

The invention provides a layout fast reading method. The layout fast reading method comprises the following steps: a GDSII file is read in, unit head information is read to build containers for units, an indexing relation between the units is built to find out a top-level unit, and pixel information of each unit is read. Correspondingly, the invention further provides a layout overall information storage device. The layout overall information storage device comprises a basic data structure for the units, containers storing unit basic structures, a linked list of subunits and a complete unit index. In this way, the operating efficiency of application programs is improved, the memory usage of the application programs is reduced, the flexibility of the application programs is improved, logic operations of the application programs are clearer, and the indexing relation is simpler.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a method for quickly reading layouts. Background technique [0002] As the manufacturing process of mainstream IC foundries gradually shifts to below the 90nm node, the magnitude of process deviation has changed from negligible to comparable to the feature size. This has led to the impact of process deviation on the performance of devices and circuits to the extent that it has to be considered. Therefore, the problem is how to estimate the process deviation that affects the performance of device circuits so as to improve or eliminate unfavorable design factors in advance. According to the demand in this respect, simulation software that imitates each process node has emerged. For example, lithography simulation software, chemical mechanical simulation software, etc. Its core idea simulation software is based on the characteristic value of the layout file to simulate the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 张贺陈岚
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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