Validation method, validation device and chip

Abstract

The invention discloses a validation method, a validation device and a chip. The validation method comprises the following steps: the chip receives a configuration instruction, the environment of an application-specific integrated circuit (ASIC) is simulated according to the configuration instruction, a gating clock signal is generated corresponding to each functional module in the chip, a preset clock signal and the gating clock signals are arranged on a global clock tree, and the global clock tree is used for validating the chip. The invention further provides the validation device and the chip. According to the validation method, the validation device and the chip, the gating clock control is realized independently corresponding to each functional module, so that time delay is within a controllable range, and an FPGA logic timing sequence is not affected; meanwhile, the functional modules in which the gating clock control is realized are arranged to be validated in a global clock tree mode, and the problem that a dynamic global clock tree can not be set up in an FPGA is also solved under the condition that the FPGA logic timing sequence is not affected.

Description

technical field [0001] The present invention relates to the technical field of microelectronic chips, and more specifically, to a verification method, device and chip. Background technique [0002] Verification is an important step in the design process of ASIC (Application Specific Integrated Circuits), and its main purpose is to test the function of the hardware description language (HDL, Hardware Description Language) in the ASIC design process. [0003] At present, Field Programmable Gate Array (FPGA, Field Programmable Gate Array) prototype verification, as a new verification method, is widely used because of its wide coverage and can cover parts that are difficult to verify in traditional simulation verification. However, ASIC design Generally, the gated clock scheme is adopted, and it is controlled through the mode of the global clock tree. Since the internal logic unit connection of the FPGA is fixed, the FPGA implements the gated clock, which will cause a large dela...

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Problems solved by technology

[0005] The embodiment of the present invention provides a verification method, device and chip, which solves the problem that the FPGA realizes the gate control clock, and the delay is relatively large, which seriously affects the logical timing of the FPGA, and at the same time solves the problem that the FPGA cannot dynamically build a global clock tree

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