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Wafer level packaging method and wafer

A wafer-level packaging and wafer technology, applied in the wafer-level packaging method and the field of wafers, can solve problems such as long dicing time, scratches on the surface of the structural layer 21, cracks in the sealing cap layer wafer 22, etc.

Active Publication Date: 2016-01-27
QST CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The problem with this process is that during the process of exposing the pad area during cutting, the silicon powder produced will contaminate the pad area, and the silicon slag splashed during the second cutting will seriously damage the high-speed rotating cutting knife, eventually resulting in mass production. high cost in the process
[0007] attached figure 2 The disadvantage of the prior art shown is that the process of cutting the groove 221 is very easy to cause scratches on the surface of the structural layer 21, and it also needs to bear the high risk of a large amount of silicon powder contaminating the pad 24 during cutting, and the severe vibration caused by the cutting process It is easy to cause cracks in the sealing cap layer wafer 22 and vacuum failure
In addition, the two wafer dicing times are very long, which seriously prolongs the process cycle

Method used

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  • Wafer level packaging method and wafer
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  • Wafer level packaging method and wafer

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Experimental program
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Embodiment Construction

[0021] A specific implementation of a wafer-level packaging method and a wafer provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0022] attached image 3 Shown is a schematic diagram of the steps of this specific embodiment, including: step S30, providing a laminated wafer, the laminated wafer includes a substrate wafer, a sealing cap layer wafer, and a structural layer; step S31, grinding and reducing Thinly seal the cap layer wafer to a target thickness; step S32, form a window in the seal cap layer wafer and the structural layer, the position of the window corresponds to the pad, thereby exposing the pad; step S33 , using test probes to contact the exposed pads to test the performance of electrical devices in the structural layer; Step S34 , dividing the stacked wafer at the position of the window.

[0023] attached Figure 4A To attach Figure 4E It is a schematic diagram of the process of this specific em...

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PUM

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Abstract

The invention provides a wafer level packaging method and a wafer. The method comprises the following steps: providing a laminated wafer which comprises a substrate wafer and a sealing cap layer wafer as well as a structural layer clamped between the substrate wafer and the sealing cap layer wafer, wherein the structural layer is attached to the substrate wafer through a bonding layer, at least a welding disc is arranged on the surface of the substrate wafer facing the structural layer, and a gap is reserved between the welding disc and the structural layer; grinding to reduce the sealing cap layer wafer to target thickness; and forming windows in the sealing cap layer wafer and the structural layer, wherein the windows correspond to the welding disc in position so as to expose the welding disc. The invention has the advantages that test of apparatuses can be realized in the wafer level, and power is not remained on the surface of the welding disc in subsequent cutting.

Description

technical field [0001] The invention relates to the packaging field, in particular to a wafer-level packaging method and a wafer. Background technique [0002] Among the rich and diverse MEMS products, accelerometers and gyroscopes occupy a high proportion in consumer electronics applications, especially in the huge market of smart phones. Accelerometers and gyroscopes, which are currently in great demand in the market, are generally realized by various bonding processes of the substrate layer, the structural layer and the capping layer. The lead pad (PAD) is sandwiched between the structural layer and the substrate layer or the structural layer and the encapsulation layer. Since the R&D level is limited by the yield and cost, the pads cannot be directly led out, so the pads trapped in the middle of the wafer must be exposed through a certain processing method, that is, to realize the de-cap of the pads. In order to be able to screen the wafers before mass-production packa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): B81C1/00B81B7/00
Inventor 王宇翔焦继伟
Owner QST CORP