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Reducing pattern loading effect in epitaxy

An epitaxy and semiconductor technology, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as unsatisfactory, reducing pattern load effect, and epitaxial performance impact

Active Publication Date: 2014-05-21
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as a side effect, other epitaxial properties such as composition are also affected by changes in pressure and gas flow rate
Also, reducing the amount of pattern loading effect using this method is not satisfactory

Method used

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  • Reducing pattern loading effect in epitaxy
  • Reducing pattern loading effect in epitaxy
  • Reducing pattern loading effect in epitaxy

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Experimental program
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Embodiment Construction

[0028] The making and using of embodiments of the invention are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed are exemplary only, and do not limit the scope of the invention.

[0029] Epitaxial processes for growing source and drain stressors for metal oxide semiconductor (MOS) devices are provided in accordance with various exemplary embodiments. Intermediate stages in the formation of MOS devices are shown. Variations of the embodiments are discussed. Like numbers are used to refer to like elements throughout the various views and illustrated embodiments.

[0030] figure 1 A substrate 4 is shown, which is a portion of a wafer 2 comprising a first portion located in the device region 100 and a second portion located in the device region 200 . Device regions 100 and 200 have different pattern de...

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PUM

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Abstract

The invention aims to reduce pattern loading effect in epitaxy. A method includes forming a gate stack over a semiconductor substrate, forming an opening in the semiconductor substrate and adjacent to the gate stack, and performing a first epitaxy to grow a first semiconductor layer in the first opening. An etch-back is performed to reduce a thickness of the first semiconductor layer. A second epitaxy is performed to grow a second semiconductor layer over the first semiconductor layer. The first and the second semiconductor layers have different compositions.

Description

technical field [0001] The present invention relates to semiconductor devices, and more particularly to epitaxial processes. Background technique [0002] Over the past few decades, the reduction in size and inherent characteristics of semiconductor devices (eg, metal-oxide-semiconductor (MOS) devices) has enabled integrated circuits with continuous improvements in speed, performance, density, and cost per function. Depending on the design of the MOS device and one of its inherent characteristics, adjusting the length of the channel region below the gate between the source and drain of the MOS device changes the resistance associated with the channel region, thereby affecting the performance of the MOS device. More specifically, reducing the length of the channel region to reduce the source-to-drain resistance of a MOS device, assuming other parameters remain relatively constant, allows the source and drain to The current between the poles increases. [0003] In order to f...

Claims

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Application Information

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IPC IPC(8): H01L21/20H01L21/336
CPCH01L21/823412H01L21/823425H01L21/823807H01L21/823814H01L21/0245H01L21/02639H01L21/02532H01L21/0262H01L29/66636H01L29/78H01L29/7848H01L29/0843H01L29/165
Inventor 宋学昌郭紫微陈冠宇李昆穆
Owner TAIWAN SEMICON MFG CO LTD