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Method for inserting filling graphs in map

A graphics and layout technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve problems such as heavy workload and long time

Active Publication Date: 2014-06-11
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In this way, the workload will be relatively large, the time will be relatively long, and there will be certain risks.

Method used

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  • Method for inserting filling graphs in map
  • Method for inserting filling graphs in map
  • Method for inserting filling graphs in map

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0024] see figure 1 , the method for inserting filling graphics in the layout of the present application includes the following steps:

[0025] The first step is to read the layout data, for example, read the layout data in GDSII format in binary mode. Different manufacturing processes define the number of local regions included in a layout, and the size of each local region. According to the layout data, the structures that allow the insertion of filling patterns in each local area are found.

[0026] There are many layers on a silicon wafer manufactured with semiconductor devices, and it is only a small part of the layers that need to insert filling patterns to meet the requirements of the CMP process. For this small portion of the hierarchy, process rules determine which blanks allow the insertion of fill graphics and which blanks do not. As for other levels, some levels are forbidden to insert filling graphics of other levels. Through the calculation of the entire lay...

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Abstract

The invention discloses a method for inserting filling graphs in a map. The method comprises the steps of virtually inserting standard filling graphs in a structure allowing the insertion of the filling graphs in every local area; calculating the graph density of the local area after virtual insertion of the filling graphs, and judging whether the graph density of the local area is larger than equal to the lowest requirement of the graph density of the local area; if the graph density of the local area is larger than equal to the lowest requirements of the graph density of the local area, practically inserting the filling graphs in the structure allowing the insertion of the filling graphs in the local area; if the graph density of the local area is small than the lowest requirement of the graph density of the local area, virtually inserting new filling graphs larger than the filling graphs virtually inserted last time; and continuously repeating the operation until the graph density of the local area after the insertion of the new filling graphs are larger than or equal to the lowest requirements of the graph density of the local area. According to the method, the insertion of the filling graphs in the map can be achieved rapidly, and all the local areas can meet the lowest graph density requirements.

Description

technical field [0001] The present application relates to a physical layout design method of a semiconductor integrated circuit, in particular to a method of inserting a filling pattern into a blank area of ​​the layout in order to meet the requirements of the CMP process. Background technique [0002] The CMP (Chemical Mechanical Polishing) process is one of the most important processes in the production of semiconductor integrated circuits, and is used to planarize the surface of silicon wafers. [0003] In the manufacture of deep submicron large-scale integrated circuits, the unevenness of the pattern density of the semiconductor physical layout will have an adverse effect on the characteristics of the manufactured circuit devices. In order to improve the yield rate of chip production, the graphic density of the layout is required to reach at least a minimum value in the CMP process. If the pattern density of the layout does not reach the minimum value, increase the patt...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 李彦正周京英孙长江
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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