Metal interconnection splicing layout structure

Abstract

The invention provides a metal interconnecting wire splicing layout structure. The metal interconnecting wire splicing layout structure comprises a first splicing module and a second splicing module, wherein the first splicing module forms a first kind of interconnecting metal interconnecting wire graphs, and the second splicing module forms a second kind of interconnecting metal interconnecting wire graphs. Connector graphs with wire widths larger than those of the second kind of interconnecting metal interconnecting wire graphs are arranged on fixed wire lengths of splicing ends of the first kind of interconnecting metal interconnecting wire graphs, the splicing ends of the second kind of interconnecting metal interconnecting wire graphs are provided with alignment overlapping areas with the wire lengths no larger than those of the connector graphs, and the connector graphs are in alignment overlapping with the second kind of interconnecting metal interconnecting wire graphs in the alignment overlapping areas when the first splicing module is spliced with the second splicing module. Through the connector graphs and the alignment overlapping of the alignment overlapping areas, the problem of splicing defects caused by metal interconnecting wire alignment malposition in the metal interconnecting wire splicing process of two chips is solved, stability of a splicing process is improved, and the product yield and performance are improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a splicing layout structure of metal interconnection lines. Background technique [0002] Deposit metal thin film on the integrated circuit chip, and form wiring through photolithography technology, and interconnect the components isolated from each other into the required circuit according to certain requirements. The requirements for metal materials used for interconnection of integrated circuits are: low resistivity, good low-ohmic contact with the electrode of the component; good adhesion to the silicon dioxide layer; easy deposition and photolithography processing to form wiring Wait. [0003] At present, in VLSI, the packaging density continues to increase to make circuit components denser and denser. However, due to the limitation of the reticle size in the chip manufacturing process, it is difficult to break through the single chip size (chipsize), so...

AI Technical Summary

Problems solved by technology

Currently, the photolithography process is limited by the size of the mask

[0004] However, due to the limitations of the structure and line width of the traditional back-end metal interconnection line and the accuracy of splicing alignment, the splicing of two chips is prone to splicing defects, which seriously affects the performance of integrated circuits.

E.g Figure 1A and 1B The metal interconnection wires of the two spliced ​​chips are not spliced ​​at all and the electrical connection is disconnected, causing the integrated circuit device to fail to work; Figure 1C The metal interconnection lines of the two spliced ​​chips have been spliced, but because the line width at the connection is very narrow, a large resistance is generated, which seriously affects the operation of the device

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