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A controller and decoder technology, used in instruments, forward error control use, static memory, etc., can solve all the problems that cannot suppress the deterioration of error correction capability, and it is difficult to cope with the stress of memory cells of non-volatile semiconductor memory. And other issues

Active Publication Date: 2017-09-29
키오시아가부시키가이샤
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  • Claims
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Problems solved by technology

[0003] Even if several representative stresses (for example, PD (Program Disturb, program disturbance), DR (Data Retention, data retention), RD (Read Disturb, read disturbance) etc.) It is still difficult for the LLR table to cope with all the various stresses that the memory cell of the nonvolatile semiconductor memory may be subjected to.
That is, even if a plurality of LLR tables are prepared in advance, there is a possibility that the deterioration of the error correction capability cannot be suppressed under some unexpected stresses (for example, a composite stress of DR stress and RD stress)

Method used

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no. 1 Embodiment approach ）

[0017] The controller 100 according to the first embodiment is, for example, figure 1 As illustrated, a decoder 101 , a channel matrix generator 102 and firmware 103 are provided. The controller 100 reads data stored in the NAND memory 110, and corrects errors contained in the read data. In addition, the controller 100 may also have, for example, a function of performing error correction coding on data, and a function of writing error correction coded data (that is, an ECC (Error Correction Code, error correction code) frame) into the NAND memory 110 . Wait.

[0018] The decoder 101 inputs and reads data from the NAND memory 110 in units of ECC frames. The read data includes not only hard decision bit values ​​for each of a plurality of bits forming the ECC frame but also a plurality of (for example, three) soft decision bit values ​​for each of these plurality of bits. In other words, the read data indicates the read level of each of the plurality of bits forming the ECC f...

no. 2 Embodiment approach ）

[0054] The controller according to the second embodiment differs from the controller according to the above-mentioned first embodiment in the operation related to DLE. Specifically, the controller according to the first embodiment generates a channel matrix based on one or more successfully decoded LDPC frames when DLE is executed. The controller according to this embodiment does not need to perform decoding accompanying the execution of DLE. Specifically, the controller according to the present embodiment generates a channel matrix based on one or more LDPC frames corresponding to known data (hereinafter referred to as known LDPC frames).

[0055] The controller 100 according to the second embodiment is, for example, figure 1 As illustrated, a decoder 101 , a channel matrix generator 102 and firmware 103 are provided. The controller 100 reads data stored in the NAND memory 110, and corrects errors contained in the read data.

[0056]The channel matrix generation unit 102 i...

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Abstract

According to one embodiment, a controller includes a generator and a creator. The generator generates a channel matrix by counting a number of times a combination of a correct bit value and a read level appears for each bit forming a decoded first frame, based on readout data indicating a read level of each of a plurality of bits forming a frame and the decoded frame. The creator creates a table by statistically calculating a likelihood of a correct bit value of each read level based on the channel matrix.

Description

technical field [0001] Embodiments relate to a controller of a nonvolatile semiconductor memory. Background technique [0002] Read data read from a nonvolatile semiconductor memory is usually converted to a log-likelihood ratio (LLR; Log-Likelihood Ratio) in accordance with a previously created table called an LLR table, and error correction is performed. The likelihood of written data (that is, a correct bit value) relative to read data varies depending on the stress applied to the storage region of the read data. [0003] Even if several representative stresses (for example, PD (Program Disturb, program disturbance), DR (Data Retention, data retention), RD (Read Disturb, read disturbance) etc.) It is still difficult for the LLR table to cope with all the various stresses that a memory cell of a nonvolatile semiconductor memory may be subjected to. That is, even if a plurality of LLR tables are prepared in advance, there is a possibility that the deterioration of the err...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/10
CPCG06F11/1048G06F11/1008G06F11/1044G06F11/1068G06F11/1076G11C7/1006H03M13/11H03M13/2957H03M13/3927H03M13/45H04L1/0041H04L1/0057H04L1/0061H04L1/0072
Inventor 樱田健次内川浩典
Owner 키오시아가부시키가이샤
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