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Chip arrangement and chip package

A chip packaging and chip technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve the problems of multi-board space assembly costs and other issues

Active Publication Date: 2014-08-06
INFINEON TECH AUSTRIA AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, discrete packages require more board space and greater assembly cost for electrical and / or thermal redistribution, such as in a standard half-bridge circuit

Method used

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  • Chip arrangement and chip package
  • Chip arrangement and chip package
  • Chip arrangement and chip package

Examples

Experimental program
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Embodiment Construction

[0015] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced.

[0016] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0017] The word "coupled" is used herein to indicate that two elements co-operate or interact with each other whether they are in direct or indirect contact (eg, physical or electrical contact).

[0018] Various embodiments relate to a chip arrangement. The chip arrangement may include: a first chip including a first contact and a second contact; a second chip; a lead frame including a first lead frame portion and an electrical contact with the first lead frame portion. an insulated second lead frame portion; and a plurality of pins ...

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Abstract

Various embodiments provide a chip arrangement. The chip arrangement may include a first chip including a first contact and a second contact; a second chip; a leadframe including a first leadframe portion and a second leadframe portion electrically insulated from the first leadframe portion; and a plurality of pins coupled to the leadframe. At least one first pin is coupled to the first leadframe portion and at least one second pin is coupled to the second leadframe portion. The first contact of the first chip is electrically coupled to the first leadframe portion and the second contact of the first chip is coupled to the second leadframe portion. A contact of the second chip is electrically coupled to the second leadframe portion.

Description

technical field [0001] Various embodiments generally relate to a chip arrangement and a chip package. For example, various embodiments relate to a multi-chip through-hole package. Background technique [0002] Multiple power semiconductor chips can be integrated into an electronic package such as a through-hole package (THP) or a surface mount device (SMD). [0003] Currently, discrete through-hole packages (eg, TO218, TO220, TO247, TO251) are used for discrete power semiconductor chips in power applications, eg, mainly for high voltage applications greater than 200V. However, discrete packaging requires more board space and greater assembly cost for electrical and / or thermal redistribution, such as in a standard half-bridge circuit. [0004] It is desirable to provide multi-chip packages for use in power applications. Contents of the invention [0005] Various embodiments provide a chip arrangement. The chip arrangement may include: a first chip including a first cont...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31
CPCH01L24/97H01L2224/4903H01L23/49562H01L23/4952H01L23/49575H01L2224/48247H01L2924/13091H01L2924/13062H01L2924/1306H01L2924/13055H01L2924/1305H01L2224/0603H01L2224/48472H01L2924/00
Inventor R·奥特雷姆巴K·希斯W·肖尔茨T·S·李F·布鲁齐D·乔拉W·佩恩霍普夫F·施蒂克勒
Owner INFINEON TECH AUSTRIA AG