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Routing method and system for a three-dimensional integrated circuit on-chip network

An integrated circuit, network-on-chip technology

Active Publication Date: 2018-03-30
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0011] The purpose of the present invention is to provide a routing method and system for a three-dimensional integrated circuit on-chip network, so as to overcome the problem that the communication performance, reliability and system overhead of the on-chip network in the prior art cannot be balanced

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[0065] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

[0066] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0067] The object of the present invention is to provide a routing method for a three-dimensional integrated circuit on-chip network. It can ensure the normal operation of communication in the case of permanent failure of the vertical connection of the three-dimensional integrated circuit on-chip network, and better balance the three indicators of high communication performance, reliability and low system overhead.

[0068] The present invention provides a routing method for a three-dimensional integrated circuit on-chip network. Generally speaking, it is a one-way communication process in which a device layer where a source node is located routes data packets ...

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Abstract

The invention discloses a routing method for a three-dimensional integrated circuit on-chip network. The optimal route of the node to ensure that the data packet reaches the destination node through the optimal route; the data routing step is used based on the principle of illegal steering between the layers of the horizontal device layer and the constraints of the corresponding steering restrictions in the vertical plane, and the routing strategy is used to transfer the data The packet is gradually routed from the source node to the destination node through the intermediate node. The invention also discloses a routing system of the three-dimensional integrated circuit on-chip network.

Description

technical field [0001] The invention relates to the field of integrated circuit reliability design, in particular to a routing method and system for a three-dimensional integrated circuit on-chip network. Background technique [0002] Three-dimensional integration technology is a packaging technology that stacks different device layers of a chip and vertically integrates them together. In the journal "proceedings of the IEEE, Volume:89, Issue:5, 2001, pp.602-633", entitled "3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration", authored by: Banerjee K. et al., discloses that this technology can shorten the length of physical connections in the chip, and achieve the effect of reducing system delay and power consumption. figure 1 It is a schematic diagram of a simple 4*2*3 three-dimensional chip network, and the topology is a common three-dimensional Mesh structure. Such as figure 1 As shown, there are 3 diff...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/701G06F15/173
Inventor 周君李华伟李晓维
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI