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Method for processing a carrier and a carrier

A carrier, hollow technology, applied in the direction of electrical solid devices, semiconductor devices, semiconductor/solid device manufacturing, etc., can solve problems such as instability

Active Publication Date: 2014-12-17
INFINEON TECH DRESDEN
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Commonly used alignment marks may not be stable at high processing temperatures, e.g. greater than 1000°C

Method used

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  • Method for processing a carrier and a carrier
  • Method for processing a carrier and a carrier
  • Method for processing a carrier and a carrier

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Embodiment Construction

[0014] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced.

[0015] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0016] The word "over" as used with respect to a deposited material formed "on" a side or surface may be used herein to mean that the deposited material may be formed directly on, eg in direct contact with, the implied side or surface. The word "over" as used with respect to deposited material formed "on" a side or surface may be used herein to mean that deposited material may be formed indirectly on the implied side or surface, wherein on the implied side or surface Or one or more additional layers are arranged between the surface an...

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Abstract

A method for processing a carrier may include forming at least one recess structure at least one of over and in the carrier; and annealing the at least one recess structure such that at least one hollow chamber is formed by material of the at least one recess structure, wherein the at least one hollow chamber may form an optical alignment structure.

Description

technical field [0001] Various embodiments relate generally to methods for processing supports, supports and methods for forming optical alignment structures in supports for lithographic processes. Background technique [0002] Fabricating chips or integrated circuits may generally include various layering and patterning processes, for example in order to handle power chips, and thus multiple alignments are necessary during processing. According to this, during various processes, such as during layering, patterning or ion implantation, the alignment marks used for carrier positioning may degrade during said processes; and thus may be of lower quality Visible, and possibly detectable with less accuracy, so that the alignment marks may need to be refreshed several times during fabrication of the chip. In various processes, the alignment marks may be covered with additional material, and thus the alignment marks may not be suitable to enable accurate alignment. Commonly used ...

Claims

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Application Information

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IPC IPC(8): H01L21/68
CPCH01L23/544H01L2223/5442H01L2223/54426H01L2223/54453H01L2223/5446H01L2924/0002
Inventor D.布迈斯特A.格赖纳T.豪克D.凯泽N.莫尔加纳A.西雷C.韦特齐希
Owner INFINEON TECH DRESDEN