An FPGA-based on-orbit reconfiguration system and method for a satellite mission computer

Abstract

An FPGA-based on-orbit reconfiguration system for a satellite computer, including a star FPGA chip with an internal CPU core; a control FPGA chip for receiving the required configuration for on-orbit reconfiguration uploaded by a communication module of the satellite The files are transferred to a SPI flash memory unit, and the on-orbit reconstruction of the Starworks FPGA chip is controlled; the SPI flash memory unit is used to store the configuration files required for on-orbit reconstruction; among them, the JTAG configuration mode is running to realize the on-orbit When reconfiguring, the control FPGA chip reads the configuration file required for the JTAG configuration mode from the SPI flash memory unit, and sends the configuration data to the star service FPGA chip; when running the SPI configuration mode to realize on-orbit reconstruction, the control FPGA chip notifies the star The service FPGA chip starts the SPI configuration mode, and the star service FPGA chip reads the configuration file required for the SPI configuration mode from the SPI flash memory unit.

Description

technical field [0001] The invention relates to the fields of aerospace and electronic science and technology, in particular, an on-orbit reconstruction system and method for a micro-nano-satellite mission computer based on a Flash-type FPGA. Background technique [0002] With the rapid development of aerospace and electronic science and technology, low-cost, low-weight, high-functional-density micro-nano satellite technology has become a hot topic in the aerospace field. Micro-nano satellites have been widely used in many fields such as earth observation, electronic reconnaissance, communication, navigation, space science detection, space detection and new technology experiments, and have become an important part of space technology. [0003] The on-board computer (OBC) of the micro-nano satellite usually uses a single-chip microcomputer based on a central processing unit chip (CPU) combined with certain peripheral circuits to realize real-time on-board data processing (OBD...

AI Technical Summary

Problems solved by technology

Usually, the JTAG configuration port of the flash FPGA can be connected to a computer and reconfigured through the development platform software. However, once the satellite is launched, the FPGA cannot be configured using the JTAG port again.

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