Voltage Mode Sensing for Low Power Flash Memory

Abstract

An electrically erasable flash memory has a memory array (50) including at least one row (24, 44) of memory cells (10, 30). Each memory cell has a data state. A voltage sensing circuit (54) is selectively coupled to individual ones of the memory cells and configured to bias them with at least one of a bias current and a bias resistance to read the data state of selected individual memory cells. The reference bit line (66) provides an indication to the sense circuit (54) that data on the selected bit line (26) can be accurately read.

Description

technical field [0001] The present invention relates generally to memory arrays and, more particularly, to memory modules comprising flash memory and ROM memory cells with common addressing circuitry. Background technique [0002] In contrast to volatile data bits, non-volatile data bits retain stored digital data for relatively long periods of time without the need to maintain power to the data bits. Such nonvolatile data bits include read-only data bits, which are made of various semiconductor devices and are known in the art as ROM, and flash data bits, which are usually made of floating gate transistors. For example, such nonvolatile data bits are electrically addressable and are therefore faster to access than mechanically addressed data storage systems such as magnetic storage (eg, hard disk) and optical storage (eg, CD-ROM). However, non-volatile data bits have historically been disadvantaged compared to volatile memory and mechanically addressed data storage in term...

AI Technical Summary

Problems solved by technology

However, the use of flash memory cells can still result in undesirably high power consumption, especially in applications that rely on low power consumption

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