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Semiconductor integrated circuit device

A technology of integrated circuits and semiconductors, applied in the field of semiconductor integrated circuit devices, which can solve the problems of inability to physically clone semiconductor chips, non-physical clones, clones, etc.

Active Publication Date: 2018-12-21
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The problem in this case is that there is a risk that the data stored at the time of manufacture will be tampered with in actual use or that the semiconductor chip itself will be cloned
According to such a proposal, it is possible to generate a unique ID of a semiconductor chip that cannot be physically cloned (PUF: Physically Unclonable Function)

Method used

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  • Semiconductor integrated circuit device
  • Semiconductor integrated circuit device
  • Semiconductor integrated circuit device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0038] figure 2 is a block diagram showing the configuration of the semiconductor integrated circuit device according to the first embodiment. exist figure 2 in, by figure 1 The same parts are denoted by the same reference numerals. exist figure 2 In, reference numeral 200 denotes a booster circuit (voltage generating circuit), and reference numeral 202 denotes a voltage wiring line to which the voltage boosted by the booster circuit 200 is supplied. In addition, in figure 2 In this, reference numeral 203 denotes a power supply voltage terminal provided in the semiconductor chip 100, and reference numeral 201 denotes a power supply voltage VDD for supplying the power supply voltage terminal to each circuit block formed in the semiconductor chip 100. power supply voltage wiring. exist figure 2 Among them, the supply voltage connection line 201 is coupled to the CPU 101 , the SRAM 103 , 104 and the booster circuit 200 . Although in figure 2 It is not shown in , b...

no. 2 example

[0068] Figure 5 is a block diagram showing the configuration of the SRAM according to the second embodiment. Figure 5 The configuration of the SRAM shown with the figure 2 with 3 The SRAM shown in is similar. exist Figure 5 in, with figure 2 with 3 The same parts are denoted by the same reference numerals, and differences will be mainly described.

[0069] If using image 3 As depicted, the cell array 300 includes a plurality of memory cells M arranged in a matrix. In the second embodiment, the feeding of the supply voltage VDD and / or the ground voltage GND to the memory cell M is controlled by the unique ID generation instruction signal 105 .

[0070] exist Figure 5 Among them, the cell power supply control circuit (voltage control circuit) 500 receives the unique ID generation instruction signal 105 and controls feeding of the power supply voltage VDD (ground voltage GND) to the cell array 300 . In the second embodiment, the unit power supply control circuit ...

no. 3 example

[0097] Figures 10A to 10C is a circuit diagram showing the configuration of the semiconductor integrated circuit device according to the third embodiment.

[0098] In the above embodiments, the SRAM incorporated in the semiconductor integrated circuit device has been described by way of example. In the third embodiment, an example in which a nonvolatile memory is used instead of an SRAM will be described. Figures 10A to 10C The configuration of cells in the nonvolatile memory is shown.

[0099] Although not limited, the semiconductor integrated circuit device according to the third embodiment includes two types of nonvolatile memories. That is, the semiconductor integrated circuit device includes a nonvolatile memory for storing data in advance and a nonvolatile memory for generating a unique ID. Instead of using non-volatile memory for storing data in advance such as figure 1 SRAM 104 in , while using non-volatile memory for unique ID generation instead figure 1 SRAM...

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PUM

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Abstract

Provided is a semiconductor integrated circuit device capable of generating a unique ID with overhead suppression. When the unique ID is generated, the potential of the word line of the memory cell in the SRAM rises above the power supply voltage of the SRAM, and then falls below the power supply voltage of the SRAM. When the potential of the word line is higher than the supply voltage of the SRAM, the same data is provided to the two bit lines of the memory cell. Thus, a memory cell in an SRAM is put into an undefined state and then changes to hold data according to the characteristics, etc. of the elements forming the memory cell. When an SRAM is manufactured, characteristics and the like of elements forming a memory cell change. Therefore, memory cells in SRAM hold data based on variations that occur during manufacturing.

Description

[0001] Cross References to Related Applications [0002] The disclosure of Japanese Patent Application No. 2013-154883 filed on July 25, 2013 including specification, drawings and abstract is hereby incorporated by reference in its entirety. technical field [0003] The present invention relates to a semiconductor integrated circuit device, in particular to a semiconductor integrated circuit device including a memory circuit and a microprocessor. Background technique [0004] There is a semiconductor integrated circuit device including a memory circuit and a microprocessor (hereinafter referred to as CPU). For example, there is a semiconductor integrated circuit device called a so-called SoC (System on Chip), which is obtained by forming a memory circuit and a CPU on one semiconductor chip. Such semiconductor circuit devices are used in many fields. [0005] Recently, the market for electronic commerce services implemented through the Internet, such as e-commerce and Inte...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/413
CPCG11C11/417G11C11/418G11C11/419G11C17/12
Inventor 薮内诚藤原英弘
Owner RENESAS ELECTRONICS CORP
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