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A Combinatorial Logic Optimization Method and System in High-Level Synthesis

A high-level synthesis and combinational logic technology, applied in the field of combinational logic optimization methods and systems in high-level synthesis, can solve problems such as redundant combinational logic operations, reduce hardware design parallelism, and affect hardware timing performance, and improve performance. , the effect of reducing redundancy

Active Publication Date: 2017-12-05
SUN YAT SEN UNIV
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  • Claims
  • Application Information

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Problems solved by technology

This will cause two problems: 1. The combinatorial logic operations in the high-level synthesis process are not optimized in depth, so there will be redundant combinatorial logic operations, which will cause too many clocks to be allocated to the hardware design during the scheduling process. cycle, thus affecting the timing performance of the generated hardware; 2. Since the underlying information of the hardware is not introduced in the high-level synthesis process, in order to prevent the hardware generated by the high-level synthesis tool from not meeting the timing and resource requirements of the design, it is necessary to perform combinatorial logic operations Pessimistic estimates of the latency and resource overhead of the design can lead to unnecessary clock cycles allocated to the design during the scheduling process, affecting the data throughput of the generation hardware, and resulting in less hardware being allocated to the design during the resource allocation process resources, thereby reducing the parallelism of hardware design and affecting the running speed of hardware

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  • A Combinatorial Logic Optimization Method and System in High-Level Synthesis
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  • A Combinatorial Logic Optimization Method and System in High-Level Synthesis

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Embodiment Construction

[0039] Such as figure 1 As shown, a combinatorial logic optimization method in high-level synthesis, the method includes:

[0040] A. Obtain the high-level functional description of the circuit design, and then obtain the various operations contained in the circuit design and the data dependencies between each operation;

[0041] C. Optimize the combinatorial logic operations with data dependencies, perform lookup table mapping according to the optimized results, and then build a lookup table operation network;

[0042] D. Use the constructed lookup table operation network to replace the combinational logic operations with data dependencies, so as to realize the reconstruction of operations.

[0043] According to different actual conditions, the lookup table operation network includes one lookup table operation, or the lookup table operation network includes more than two lookup table operations.

[0044] Further as a preferred embodiment, the step D includes:

[0045] D1. ...

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Abstract

The invention discloses a combined logic optimization method and system in high-level synthesis. The system includes an acquisition unit, a combined logic optimization mapping unit and a reconstruction unit. The method includes: obtaining each operation of the circuit design and the data dependency between each operation; optimizing the combined logic operation with the data dependency, performing lookup table mapping according to the optimized result, and then constructing a lookup table operation network; A network of lookup table operations is used to replace the combinational logic operations with data dependencies. The present invention can optimize the combinatorial logic in the design at the high-level synthesis stage, remove redundant combinatorial logic operations, and introduce underlying hardware information into the high-level synthesis by adding a lookup table operation, providing more accurate information for subsequent high-level synthesis steps. Combination logic delay and resource overhead information can help improve the performance of high-level synthesis tools. The invention can be widely applied in the field of hardware design.

Description

technical field [0001] The invention relates to the field of hardware design, in particular to a combinational logic optimization method and system in high-level synthesis. Background technique [0002] High-level synthesis includes steps such as compilation, optimization, scheduling, resource allocation, and controller synthesis. After the high-level language is compiled and optimized, it is translated into a low-level intermediate expression, which is used as input for subsequent high-level synthesis steps such as scheduling and resource allocation. [0003] At present, the research hotspots of high-level synthesis projects are mainly focused on scheduling, resource allocation, and controller synthesis, while steps such as combinatorial logic optimization and process mapping are handed over to subsequent FPGA logic synthesis tools. In the process of hierarchical synthesis, in-depth optimization of combinatorial logic operations in the design is not involved, and the under...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 陈弟虎王自鑫袁悦来涂玏郑洪滨
Owner SUN YAT SEN UNIV
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