A Combinatorial Logic Optimization Method and System in High-Level Synthesis

Abstract

The invention discloses a combined logic optimization method and system in high-level synthesis. The system includes an acquisition unit, a combined logic optimization mapping unit and a reconstruction unit. The method includes: obtaining each operation of the circuit design and the data dependency between each operation; optimizing the combined logic operation with the data dependency, performing lookup table mapping according to the optimized result, and then constructing a lookup table operation network; A network of lookup table operations is used to replace the combinational logic operations with data dependencies. The present invention can optimize the combinatorial logic in the design at the high-level synthesis stage, remove redundant combinatorial logic operations, and introduce underlying hardware information into the high-level synthesis by adding a lookup table operation, providing more accurate information for subsequent high-level synthesis steps. Combination logic delay and resource overhead information can help improve the performance of high-level synthesis tools. The invention can be widely applied in the field of hardware design.

Description

technical field [0001] The invention relates to the field of hardware design, in particular to a combinational logic optimization method and system in high-level synthesis. Background technique [0002] High-level synthesis includes steps such as compilation, optimization, scheduling, resource allocation, and controller synthesis. After the high-level language is compiled and optimized, it is translated into a low-level intermediate expression, which is used as input for subsequent high-level synthesis steps such as scheduling and resource allocation. [0003] At present, the research hotspots of high-level synthesis projects are mainly focused on scheduling, resource allocation, and controller synthesis, while steps such as combinatorial logic optimization and process mapping are handed over to subsequent FPGA logic synthesis tools. In the process of hierarchical synthesis, in-depth optimization of combinatorial logic operations in the design is not involved, and the under...

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Problems solved by technology

This will cause two problems: 1. The combinatorial logic operations in the high-level synthesis process are not optimized in depth, so there will be redundant combinatorial logic operations, which will cause too many clocks to be allocated to the hardware design during the scheduling process. cycle, thus affecting the timing performance of the generated hardware; 2. Since the underlying information of the hardware is not introduced in the high-level synthesis process, in order to prevent the hardware generated by the high-level synthesis tool from not meeting the timing and resource requirements of the design, it is necessary to perform combinatorial logic operations Pessimistic estimates of the latency and resource overhead of the design can lead to unnecessary clock cycles allocated to the design during the scheduling process, affecting the data throughput of the generation hardware, and resulting in less hardware being allocated to the design during the resource allocation process resources, thereby reducing the parallelism of hardware design and affecting the running speed of hardware

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