Combinational logic optimization method and system in high-level synthesis

Abstract

The invention discloses a combinational logic optimization method and system in high-level synthesis. The combinational logic optimization system in the high-level synthesis comprises an obtaining unit, a combinational logic optimization mapping unit and a reconstruction unit. The combinational logic optimization method in the high-level synthesis comprises the following steps of obtaining operations designed in a circuit and a data dependence relationship between the operations; optimizing the combinational logic operations having the data dependence relationship, performing lookup table mapping according to an optimized result, and accordingly constructing a lookup table operation network; replacing the combinational logic operations having the data dependence relationship with the lookup table operation network. The combinational logic optimization method and system in the high-level synthesis can optimize the designing combinational logic in a high-level synthesis stage, remove redundant combinational logic calculations, introduce bottom layer hardware information to the high-level synthesis by adding the lookup table operation, provide more accurate combinational logic time delay and resource expenditure information for a follow-up high-level synthesis step, are beneficial to improvement of performance of each high-level synthesis tool, and can be widely applied to the hardware design field.

Description

technical field [0001] The invention relates to the field of hardware design, in particular to a combinational logic optimization method and system in high-level synthesis. Background technique [0002] High-level synthesis includes steps such as compilation, optimization, scheduling, resource allocation, and controller synthesis. After the high-level language is compiled and optimized, it is translated into a low-level intermediate expression, which is used as input for subsequent high-level synthesis steps such as scheduling and resource allocation. [0003] At present, the research hotspots of high-level synthesis projects are mainly focused on scheduling, resource allocation, and controller synthesis, while steps such as combinatorial logic optimization and process mapping are handed over to subsequent FPGA logic synthesis tools. In the process of hierarchical synthesis, in-depth optimization of combinatorial logic operations in the design is not involved, and the under...

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Problems solved by technology

This will cause two problems: 1. The combinatorial logic operations in the high-level synthesis process are not optimized in depth, so there will be redundant combinatorial logic operations, which will cause too many clocks to be allocated to the hardware design during the scheduling process. cycle, thus affecting the timing performance of the generated hardware; 2. Since the underlying information of the hardware is not introduced in the high-level synthesis process, in order to prevent the hardware generated by the high-level synthesis tool from not meeting the timing and resource requirements of the design, it is necessary to perform combinatorial logic operations Pessimistic estimates of the latency and resource overhead of the design can lead to unnecessary clock cycles allocated to the design during the scheduling process, affecting the data throughput of the generation hardware, and resulting in less hardware being allocated to the design during the resource allocation process resources, thereby reducing the parallelism of hardware design and affecting the running speed of hardware

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