Digital calibration method and circuit of multi-level multi-bit sub-circuit in analog-to-digital converter

Abstract

The invention relates to a digital calibration method for a multi-stage multi-bit sub-circuit in an analog-to-digital converter. First, a peripheral control circuit is designed to control the working state of the ADC so that it can control the sub-level circuits that need to be calibrated, and the The error output of each sub-level stored in the ADC internal register is read, and the error calculation is performed, and the calculated error value is stored in the ADC internal register, and the error calculated by each sub-level is calculated by the data synthesis module. Compensate to the final output to complete the calibration. The main advantage of the invention is that it proposes a capacitance mismatch calibration method for multi-stage multi-bit sub-circuits, which is realized by digital circuits. The calibration control process is realized outside the chip of the analog-to-digital converter, which reduces the complexity of the entire analog-to-digital converter design, the calibration method is simple and reliable, and the calibration effect is good.

Description

technical field [0001] The invention belongs to the field of integrated circuit design and manufacture, and in particular relates to a digital calibration method and circuit of a multi-stage multi-bit sub-circuit in a pipeline analog-to-digital converter. Background technique [0002] With the rapid development of microprocessors and signal processing technologies, performance requirements for analog-to-digital converters (Analog-to-Digital Converter, ADC) are getting higher and higher. High-speed and high-precision pipeline ADC is widely used in the field of signal processing because of its fast conversion speed, high resolution and low power consumption. On the other hand, with the rapid development of integrated circuit technology, the size of the device is getting smaller and smaller, the working speed of the device is further improved, and the power consumption is further reduced. However, the device mismatch caused by size reduction is getting more and more serious. W...

AI Technical Summary

Problems solved by technology

[0005] Since the multi-bit sub-level ADC uses a large number of capacitors and a large number of comparison points in the comparator, the implementation method of the analog circuit will make the circuit very complicated, and the power consumption and area will be greatly increased.

Although the existing 1.5-bit sub-ADC digital calibration technology has a good calibration effect, it cannot meet the requirements of high-precision multi-bit sub-level structure pipeline ADC design.

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