Reverse tone self-aligned contact

Abstract

Some embodiments of the present disclosure relate to a method to form a source / drain self-aligned contact to a transistor or other semiconductor device. The method comprises forming a pair of gate structures over a substrate, and forming a source / drain region between the pair of gate structures. The method further comprises forming a sacrificial source / drain contact which is arranged over the source / drain region and which is arranged laterally between neighboring sidewalls of the pair of gate structures. The method further comprises forming a dielectric layer which extends over the sacrificial source / drain contact and over the pair of gate structures. The dielectric layer differs from the sacrificial source / drain contact. The method further comprises removing a portion of the dielectric layer over the sacrificial source / drain contact and subsequently removing the sacrificial source / drain contact to form a recess, and filling the recess with a conductive material to form a source / drain contact.

Description

technical field [0001] The following disclosure relates to semiconductor manufacturing methods. In particular, the following disclosure relates to methods for forming contacts of semiconductor devices. Background technique [0002] For advanced semiconductor nodes, scaling of devices according to Moore's Law has resulted in polysilicon gate contact pitch (contacted poly pitch, CPP) (ie, the minimum center-to-center spacing between the gates of adjacent transistors) less than about 100nm. Therefore, it is necessary to place the contacts of the source or drain of such transistors within the remaining space between adjacent gates without shorting the gates to the drains. To do this, methods such as double or triple patterning of source / drain contacts have been utilized. [0003] Multiple patterning techniques require additional mask and fabrication costs than single patterning techniques. Furthermore, the use of additional masks degrades the source / drain contacts, the sourc...

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Problems solved by technology

[0003] Multiple patterning requires additional mask and fabrication costs than single patterning

Furthermore, the use of additional masks degrades the source / drain contacts, the source or drain aligned with the contacts, and adjacent features such as the gates of transistors from which the contacts must be electrically isolated to ensure yield. ) between overlay (OVL) controls

Other techniques such as forming self-aligned contacts can reduce the OVL degradation associated with multiple patterning techniques, but require additional layers in the transistor device stack to form proper contacts

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