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Transistor contacts self-aligned in two dimensions

A transistor and drain contact technology, applied in the direction of transistors, semiconductor devices, electric solid state devices, etc., can solve the problem of limiting the amount of shrinkage

Active Publication Date: 2015-10-14
GLOBALFOUNDRIES U S INC MALTA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, process issues still limit the amount of shrinkage that can be achieved
In particular, bonding the device to the metallization contacts presents many challenges

Method used

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  • Transistor contacts self-aligned in two dimensions
  • Transistor contacts self-aligned in two dimensions
  • Transistor contacts self-aligned in two dimensions

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Embodiment Construction

[0020] It will be appreciated that this disclosure may be embodied in many different forms and should not be construed as limited to the illustrative specific embodiments set forth herein. Rather, these specific embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. For example, as used herein, the singular forms "a", "an", "an", and "the" are intended to include the plural forms unless the context dictates otherwise. Also, the words "a", "an", "an", etc. do not indicate a limitation of quantity, but rather indicate that there is at least one of the referenced item. It will be further understood that the words "comprises" and / or "comprises", or "includes" and / or "includes" if used in this specification, are designating said features, ...

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PUM

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Abstract

Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source / drain coverage. Selective etch processes open the desired gates and source / drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

Description

technical field [0001] The present invention relates generally to semiconductor fabrication, and more particularly to structures and fabrication methods for transistor contacts. Background technique [0002] With the advancement of technology, the manufacture of electronic devices must be improved to meet the trend of mobile, light weight and high efficiency electronic devices. In addition to reducing the size of semiconductor devices, miniaturization can also be achieved by reducing the distance between semiconductor devices. However, process issues still limit the amount of shrinkage that can be achieved. In particular, bonding the device to the contacts of the metallization layers presents many challenges. Accordingly, it would be desirable to have improved contacting and fabrication methods. Contents of the invention [0003] Embodiments of the present invention provide improved semiconductor structures and fabrication methods that provide two-dimensional self-align...

Claims

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Application Information

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IPC IPC(8): H01L21/768
CPCH01L21/76897H01L21/02164H01L21/0217H01L21/28568H01L21/76834H01L21/823475H01L21/823878H01L23/53228H01L23/53257H01L23/5329H01L27/088H01L27/092H01L29/66462H01L21/76895H01L21/823871H01L29/41725H01L29/78H01L2924/0002H01L2924/00H01L23/528H01L29/41758
Inventor A·C-H·魏G·布赫M·A·扎勒斯基T·G·尼奥吉J·E·史蒂芬斯桂宗郁J·曾
Owner GLOBALFOUNDRIES U S INC MALTA
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