Management method of flash memory and bad blocks
A technology of flash memory and management method, applied in the field of bad block management
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[0070] Figure 4 It is a block diagram showing the structure of the flash memory of the embodiment of the present invention. However, the configuration of the flash memory shown here is an example, and the present invention is not necessarily limited to this configuration.
[0071] The flash memory 100 of the present embodiment is constituted to include: a memory array 110 forming a plurality of memory cells arranged in a matrix; an input-output buffer (buffer) 120 connected to an external input-output terminal I / O and holding input-output data ; Address register (address register) 130, receives the address data from I / O buffer 120; Data register 140, keeps the data of input and output; Controller 150, based on command data and external control signal from I / O buffer 120 The illustrated chip enable (chip enable) or address latch enable (address latch enable), etc.), and supply control signal C1, control signal C2, control signal C3, etc. to control each part; look-up table (L...
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