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Three-level cache storage apparatus and method for dynamic reconfigurable bus monitoring system

A technology of a three-level buffer and storage device, which is used in electrical digital data processing, instruments, input/output to record carriers, etc., can solve problems such as the inability to meet high-speed concurrent storage of various monitoring data.

Active Publication Date: 2015-11-11
CAPITAL NORMAL UNIVERSITY
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AI Technical Summary

Problems solved by technology

[0012] Due to the need for comprehensive monitoring of the activities on the bus, the UM-BUS bus monitoring system will generate a variety of different monitoring information including command header data, long packet data, error information, channel detection information, and even these different monitoring information Arrive at the same time, and for each type of monitoring information, it needs to be packaged and stored together with the time code and other monitoring field work data, so the conventional buffering method is used to set a buffer for each type of information, or set a general buffer for all information , cannot meet the high-speed concurrent storage of various monitoring data by the UM-BUS bus monitoring system

Method used

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  • Three-level cache storage apparatus and method for dynamic reconfigurable bus monitoring system

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specific Embodiment approach

[0033] Based on the operating principle of the above-mentioned UM-BUS bus and bus monitoring node, a kind of specific implementation of the three-level buffer storage device of the present invention is as follows:

[0034] In the bus monitoring system, set such as Figure 5 A third-level buffer storage device shown includes a bus data monitoring module, a channel detection and identification module, a timer, a first-level buffer, a second-level buffer, a third-level buffer and a host transmission control module.

[0035] The bus data monitoring module is used to continuously monitor the dynamic reconfigurable bus, and write the monitored communication information packets into the first-level buffer; when a communication error is detected, write the error information into the first-level buffer.

[0036] The channel detection and identification module is used to monitor the bus channel detection process, and write the detected detection information into the primary buffer.

[...

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Abstract

A three-level cache storage apparatus and method for a dynamic reconfigurable bus monitoring system are disclosed. The three-level cache storage apparatus is characterized by comprising a bus data monitoring module, a channel detection and identification module, a timer, a first-level cache region, a second-level cache region, a third-level cache region and a host transmission control module; and with secondary packaging, three-level caching and partition storage methods, monitored communication data, error information, detection information and the like in the dynamic reconfigurable bus monitoring system are subjected to cache storage.

Description

technical field [0001] The invention relates to a data buffer storage device in an embedded system bus monitoring system, in particular to a buffer storage device for monitoring data in a dynamically reconfigurable bus monitoring system. The invention also relates to a buffer storage method for monitoring data in a dynamic reconfigurable bus monitoring system. Background technique [0002] The dynamic reconfigurable bus (UM-BUS) is a high-speed serial bus based on M-LVDS bus topology defined for high-reliability embedded applications, such as figure 1 As shown, it adopts a bus-type topology structure, supports direct interconnection of multiple nodes, and can use up to 32 channels to transmit data concurrently. If some channels fail, the bus controller can detect them in real time, dynamically allocate data to the remaining effective channels for transmission, realize dynamic reconstruction, and dynamically fault-tolerant communication failures. [0003] The communication ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06G06F13/16
Inventor 周继芹张伟功陕天龙李超王晶邱柯妮朱晓燕徐远超
Owner CAPITAL NORMAL UNIVERSITY
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