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A Task Scheduling Method Based on Task Application Signal and Processor Core Execution Cost

A processor core and task scheduling technology, applied in multi-programming devices, program startup/switching, etc., can solve the problems of short execution time, lack of consideration of processor core performance and task characteristics, etc., to reduce overhead and achieve accurate tasks. The effect of scheduling sequential queues and reducing execution time

Active Publication Date: 2019-01-15
HARBIN ENG UNIV
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AI Technical Summary

Problems solved by technology

This on-demand scheduling method does not take into account the performance and task characteristics of the processor core, which obviously violates the basic principle of heterogeneous multi-core processors to schedule the correct task to the correct processor core, because the queue head element is scheduled to idle The core may not meet the shortest execution time of all tasks

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  • A Task Scheduling Method Based on Task Application Signal and Processor Core Execution Cost
  • A Task Scheduling Method Based on Task Application Signal and Processor Core Execution Cost
  • A Task Scheduling Method Based on Task Application Signal and Processor Core Execution Cost

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Embodiment Construction

[0022] The present invention is described in more detail below in conjunction with accompanying drawing:

[0023] The present invention provides a task scheduling method based on the task application signal and the execution cost of the processor core. The method takes how to solve the sequence of scheduling tasks as the main idea, and combines the global linked list and the processor core scheduling queue to record tasks. The probability of task scheduling to the processor core is calculated according to the strength of the task application signal and the execution cost of the processor core. Among them, the task application signal reflects the urgency of the task's expectation to be scheduled. Whenever a new task is generated, it is inserted into the tail of the global linked list, and an application signal waiting for scheduling is sent to all processor cores at the same time. On this basis, each processor core maintains an execution cost value vector, and the processor cor...

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Abstract

The invention relates to a task scheduling method based on a task application signal and an execution cost value of a processor core. The task scheduling method comprises the following steps: (1) the task application signal: a global linked list and a processor core scheduling queue are adopted to record a task; (2) the execution cost value of the processor core: each processor core maintains one execution cost value vector, and the processor core calculates to obtain the execution cost value of each task in the global linked list, and stores the execution cost value of each task into the execution cost value vector; and (3) task scheduling probability: the processor core calculates the probability for scheduling the task to the processor core scheduling queue from the global linked list according to the execution cost value of the task and the application signal of the task. The global linked list and the processor core scheduling queue are adopted to record tasks, the application signal intensity of the task and the task execution cost value of the processor core are used as task scheduling criterions, cost generated in a task transfer process can be effectively reduced, and task execution time is shortened.

Description

technical field [0001] The invention relates to a task scheduling method based on a task application signal and a processor core execution cost value. Background technique [0002] With the development of large-scale integrated circuits, the speed, power consumption and chip area of ​​transistors have been greatly improved, which has promoted the continuous improvement of the performance of single-core processors. At present, single-core processors have almost been unable to significantly increase the speed of the processor by means of technological improvements. The emergence of multi-core processors (chip multiprocessors, CMPs) that integrate multiple processor cores on the same chip has effectively solved the bottleneck of the development of single-core processors. In 2006, IBM launched the first commercial isomorphic dual-core processor POWER4. Subsequently, a series of chip manufacturers launched a series of products. According to Amdahl's law, adding a homogeneous m...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/48
Inventor 李静梅田乔毛施平
Owner HARBIN ENG UNIV
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