A construction method of high-efficiency x-structure obstacle-avoiding router for multi-layer chips

An obstacle-avoiding router and multi-layer chip technology, which is applied in instruments, special data processing applications, electrical digital data processing, etc., can solve problems such as difficult problems, and achieve the effects of compact logic, compressed line length, and increased total length of shared paths

Active Publication Date: 2018-06-15
上海立芯软件科技有限公司
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Problems solved by technology

[0005] The problem is that when considering the three factors of multi-layer chip structure, obstacles, and X-structure at the same time, that is, the multi-layer obstacle-avoiding X-architecture Steiner minimal tree (ML-OAXSMT) router construction, the problem becomes very difficult
Because, only a single-layer RSMT router construction has been proved to be an NP-complete problem

Method used

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  • A construction method of high-efficiency x-structure obstacle-avoiding router for multi-layer chips
  • A construction method of high-efficiency x-structure obstacle-avoiding router for multi-layer chips
  • A construction method of high-efficiency x-structure obstacle-avoiding router for multi-layer chips

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Embodiment Construction

[0019] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0020] A method for constructing an efficient X-structure obstacle-avoiding router for multilayer chips, comprising the following steps:

[0021] Step S1: According to a given set of pin coordinate positions, a 3D-OFMST connecting all pins is generated based on a fast multi-slice MST construction strategy, and the 3D-OFMST is the basic structure of the final ML-OAXSMT;

[0022] Step S2: The XRP information of all edges in 3D-OFMST is calculated, and these information are stored in two records to generate two lookup tables, which can provide information support for the subsequent operation of the router;

[0023] Step S3: Based on the quick table lookup, generate an ML-XST by converting each edge of the 3D-OFMST into an XRP, and convert the ML-XST into an ML-OAXST;

[0024] Step S4: Further optimize ML-OAXST from both global and local perspecti...

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Abstract

The invention relates to the technical field of integrated circuit computer-aided design, in particular to a construction method for a multi-layer-chip efficient X-structure obstacle-avoiding router. The method comprises the following steps: step S1, according to a group of given pin coordinate positions, generating a 3D-OFMST (3D Obstacle-free Minimal Spanning Tree) connected with all pins based on a fast multi-fragmentation minimal spanning tree (MST); step S2, calculating XRPs (X Routing Paths) of all edges in the 3D-OFMST, and saving the calculated information to two records to generate two lookup tables; step S3, based on the lookup tables, transforming each edge of the 3D-OFMST to an XRP to generate an ML-XST (Multi-layer X-architecture Steiner Tree), and transforming the ML-XSTs to an ML-OAXST (Multi-layer Obstacle-avoiding X-architecture Steiner Tree); step S4, further optimizing the ML-OAXST from global and local perspectives so as to generate a final ML-OAXSMT.

Description

technical field [0001] The invention belongs to the technical field of computer-aided design of integrated circuits, and in particular relates to the construction problem of a high-efficiency X-structure obstacle-avoiding router for multi-layer chips. Background technique [0002] The Steiner minimum tree is one of the most important mathematical models in the field of graph theory, and has been widely used in many research fields. In particular, the rectangular Steiner minimal tree (RSMT) proposed by Hanna in 1966 has been widely used in multiple stages of modern very large scale integration (VLSI) design. For example, in the early design stages, including partitioning, floorplanning, and placement, RSMT can be used to effectively predict multiple performance indicators of the chip, such as wire length, congestion, and delay. During the general routing and detailed routing phases, RSMT can be used to construct the final connectivity topology for each net. In addition, wit...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 郭文忠黄兴刘耿耿陈国龙
Owner 上海立芯软件科技有限公司
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