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An instruction execution method and sequential processor

A technology of instruction execution and processor, which is applied in the field of instruction processing, can solve problems such as waste of empty shots and reduce processor performance, and achieve the effect of reducing empty shots, reducing idle waiting time, and exerting performance

Active Publication Date: 2018-01-02
HUAWEI TECH CO LTD +1
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  • Claims
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Problems solved by technology

[0004] However, if empty beats are added to the pipeline, only the number of beats for executing instructions in a pipeline is effectively used in one execution cycle, and the increased empty beats will be wasted when the processor executes. At this time, the processor has no effective Instructions are processed and idle, which reduces processor performance

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  • An instruction execution method and sequential processor
  • An instruction execution method and sequential processor
  • An instruction execution method and sequential processor

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Embodiment Construction

[0056] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts belong to the protection scope of the present invention.

[0057] see figure 1 , an embodiment of the instruction execution method in the embodiment of the present invention includes:

[0058] 101. When there are a preset number of serially connected functional units in a pipeline of the sequential processor, the sequential processor determines that the preset number is the maximum number of execution beats for each instruction combination;

[0059] When there are a preset number of serially connected functional units in a pipel...

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Abstract

The embodiment of the invention discloses an instruction execution method and a sequential processor, which are used for combining instructions in the sequential processor, reducing idle time, and exerting processor performance to a greater extent. The method in the embodiment of the present invention includes: the sequential processor sequentially fuses multiple instructions into an instruction combination according to the order of instructions, wherein the sum of the execution beats of the multiple instructions is not greater than the maximum execution beats, and then sequentially emits and fuses the instructions into an instruction combination. Each combination of instructions, execute the instructions in each combination of instructions sequentially.

Description

technical field [0001] The invention relates to the field of instruction processing, in particular to an instruction execution method and a sequential processor. Background technique [0002] The current commercial processor CPUs are generally divided into two categories according to different instruction scheduling methods: in-order execution and out-of-order execution. [0003] In a processor with sequential execution, a pipeline has a fixed number of executable beats in one execution cycle, and each instruction has a certain number of execution beats. In order to submit instructions sequentially, processor designers usually design for Instructions with fewer beats are executed with a delay stage in their corresponding pipelines, so that the pipelines of these instructions with fewer beats are executed have the same number of stages as the instructions with longer execution beats, achieving the purpose of sequential submission. [0004] However, if empty beats are added t...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30G06F9/38
Inventor 张立新苏东锋陈凯柴琳
Owner HUAWEI TECH CO LTD
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