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Out-chip buffer compression method for superhigh-definition processing system

A technology for processing systems and compression methods, applied in the field of video processing, to improve read and write efficiency and reduce repeated data reading

Active Publication Date: 2016-04-06
SHANGHAI JIAO TONG UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

These characteristics are not satisfied by general-purpose codecs

Method used

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  • Out-chip buffer compression method for superhigh-definition processing system
  • Out-chip buffer compression method for superhigh-definition processing system
  • Out-chip buffer compression method for superhigh-definition processing system

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Embodiment Construction

[0061] The present invention will be described in detail below in conjunction with specific embodiments. The following examples will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0062] Such as figure 1 As shown, an off-chip cache compression method for ultra-high-definition video processing systems, including:

[0063] Step 1. Compression

[0064] Group the video frame data from the original video input terminal and the video frame data from the processing core to complete video processing functions (such as ultra-high-definition video frame rate up-conversion, video denoising, video post-processing, etc.) to form blocks to be compressed, And perform prediction, quantizat...

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Abstract

The invention provides an out-chip buffer compression method for a superhigh-definition processing system, and the method comprises the steps: compression: grouping video frame data from an original video input end and video frame data from a processing core during the completing of a video processing function so as to form a to-be-compressed block, carrying out the in-block pixel grouping, prediction, quantification, reverse quantification, pixel reconstruction, entropy coding, code stream packaging, compression simplifying and compressed code stream output control operation of each to-be-compressed block, obtaining a compressed code stream, and enabling the compressed code stream to be written into an out-chip buffer; decompression: reading a compressed code stream from the out-chip buffer, carrying out real-time decoding after code stream analysis, entropy decoding, reverse quantification, pixel forming, simplified compression decoding and pixel block restoration, forming a decompressed pixel block, and enables the decompressed pixel block to be outputted to the processing core and an output display module. The method can greatly reduce the bandwidth of the out-chip buffer, and improves the data throughput rate of the system.

Description

technical field [0001] The invention relates to the field of video processing, in particular to an off-chip cache compression method for an ultra-high-definition video processing system. Background technique [0002] In recent years, people's subjective demand for high-quality visual enjoyment and the objective conditions of the rapid development of semiconductor technology have jointly promoted the vigorous development of the video industry. High-definition 2K, ultra-high-definition 4K, and 8K video are also rapidly industrialized. Ultra-high-definition video processing systems, such as ultra-high-definition TV post-processing ASICs and ultra-high-definition video codecs, generally use a data processing core and an external dynamic memory to work together. The processing core is generally implemented by an ASIC or a coprocessor, and the off-chip memory is used to store a large amount of video data, and the processing core needs to frequently access the external memory. [...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N19/42H04N19/423H04N19/433H04N21/426H04N21/433
CPCH04N21/42692H04N21/4331
Inventor 陈立薛培培高志勇张小云郭勇
Owner SHANGHAI JIAO TONG UNIV
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