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Control time-intensive instructions

A technology of instruction and time, applied in the direction of instruction analysis, program control design, multi-program device, etc., can solve the problems of consumption or even more, inconvenience, waste of processor resources, etc.

Active Publication Date: 2020-02-28
ARM LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this will waste any processor resources already expended on that instruction, and may often need to expend even more processor resources to restore the state of the processor to what it was before the time-consuming instruction began executing
Additionally, some instructions are inherently non-interruptible or could have inconvenient adverse effects if interrupted

Method used

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  • Control time-intensive instructions
  • Control time-intensive instructions
  • Control time-intensive instructions

Examples

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Embodiment Construction

[0038] figure 1 Schematic illustration of software that may be executed in a virtualized system utilizing the techniques described herein.

[0039] The software is hierarchical and includes a hypervisor 10 executing at exception level EL2 (also known as privilege level or execution level), which hypervisor governs a number of guest operating systems executing at exception level EL1. An exception level indicates the level of privilege given to software executing at that exception level. In this example, the hypervisor executes at a higher exception level than the guest operating system, and thus the hypervisor has more privileges than the guest operating system. This particular example shows three exception levels (EL2, EL1, and EL0). However, it will be appreciated that the techniques described herein are applicable to systems containing any plural number of exception levels.

[0040] The guest operating system includes a real-time operating system 30 and a rich operating s...

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PUM

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Abstract

Running time-intensive instructions can cause critical events to be delayed or not responded to at all. The information processing apparatus includes: processing circuitry 60 for executing instructions including one or more time-intensive instructions; and exception generating circuitry 100 for generating at least one exception to the processing circuitry. The processing circuitry maintains a control value 20 indicating whether a time-intensive instruction may be executed. When a time-intensive instruction is encountered, if the control value indicates that the time-intensive instruction cannot be executed, the first exception triggers the processing circuit system to stop the execution of the time-intensive instruction. Alternatively, the time-intensive instruction is executed if the control value indicates that the time-intensive instruction can be executed.

Description

technical field [0001] The invention is directed to the field of data processing devices. More particularly, the present invention may relate to controlling time-intensive instructions in data processing devices. Background technique [0002] In real-time systems, it is often necessary to respond to a specific event within a period of time or at a specific time. To achieve this, such systems often rely on deterministic behavior of the system as a whole. For example, it may be desirable to provide software that accesses a processor or another hardware device, such as a sensor, at predetermined intervals or times. [0003] One example of a real-time system is an airbag deployment system, which is designed to detect a collision of a vehicle and deploy an airbag upon detection of such a collision. In this system, it may be necessary to deploy the airbag within a very short period of time since the collision event is detected. [0004] However, if the hardware is busy, the pr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/48
CPCG06F9/4812G06F9/4887G06F9/30145G06F9/45533G06F9/4843G06F9/3005
Inventor 西蒙·克拉斯克安东尼·彭顿
Owner ARM LTD