Logic protection device for parallel node fault of electric loop
An electrical circuit and protection device technology, applied in circuit devices, emergency protection circuit devices, electrical components, etc., can solve problems such as the failure of the bus tie switch to close and the dual power supply ring network to supply power.
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Embodiment 1
[0083] Example 1: see figure 1 Wherein, the present invention is applied in a single power supply ring network power supply network, the common point of A1, A2, B1, B2, B3 constitutes a parallel electrical node P1, similarly A3, A4, B4, B5, B6 and A5, B7, B8 and B9 constitute the parallel electrical nodes P2 and P3 respectively. For each node from P1 to P3, the logic protection of the present invention can be adopted, and the fault point and the path of fault current are as follows: Figure 6-1 and Figure 6-2 The results of the analysis are shown in Table 2.
Embodiment 2
[0084] Example 2: see figure 2 , the present invention is applied in a dual power supply ring network power supply network, the common point of (A1, A2, B1, B2, B3) constitutes a parallel electrical node P1, similarly (A3, A4, B4, B5, B6) and ( A5, A6, B7, B8, B9) form parallel electrical nodes P2 and P3 respectively. The difference from Embodiment 1 is that there is an additional incoming switch A6 of the power supply S2. The logical protection of the present invention can be adopted for each node from P1 to P3. The fault point and the path of the fault current are shown in FIG. 6 , and the faults shown in FIG. 6 exist at the same time for nodes P1 and P3. The results of the analysis are shown in Table 2.
Embodiment 3
[0085] Embodiment 3: see image 3 , the present invention is applied in a radial power supply network, (S1, A1, A4), (A2, A3, A5), (A4, B1, B2) and (A5, B3, B4) constitute the parallel electrical nodes P1 to P4. The logical protection of the present invention can be adopted for each node, and the fault point and the path of the fault current can still be equivalent to the fault of the node such as Figure 6-1 and branch faults such as Figure 6-2 The results of the analysis are shown in Table 2.
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