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Adaptive process for data sharing with selection of lock elision and locking

A hardware lock omission and address lock technology, which is used in electrical digital data processing, concurrent instruction execution, machine execution devices, etc.

Active Publication Date: 2016-06-15
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Transactions execute optimistically without acquiring locks, however, transactional execution may need to be aborted and retried if an operation of an executing transaction on a memory location conflicts with another operation on the same memory location

Method used

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  • Adaptive process for data sharing with selection of lock elision and locking
  • Adaptive process for data sharing with selection of lock elision and locking
  • Adaptive process for data sharing with selection of lock elision and locking

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Embodiment Construction

[0018] Historically, computer systems or processors have only had a single processor (aka processing unit or central processing unit). The processor includes an instruction processing unit (IPU), a branch unit, and a memory control unit. This processor is capable of executing a single thread of a program at a time. Operating systems were developed that could time share servers by allocating a program to execute on a processor for one period of time, and then allocating another program to execute on a processor for another period of time. As technology evolves, memory subsystem caches are often added to processors as well as complex dynamic address translations including translation lookaside buffers (TLBs). The IPU itself is often referred to as a processor. As technology continues to develop, an entire processor can be packaged as a single semiconductor chip or die, known as a microprocessor. Then, a processor incorporating multiple IPUs was developed, which is also often ...

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PUM

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Abstract

In a Hardware Lock Elision (HLE) Environment, predictively determining whether a HLE transaction should actually acquire a lock and execute non-transactionally, is provided. Included is, based on encountering an HLE lock-acquire instruction, determining, based on an HLE predictor, whether to elide the lock and proceed as an HLE transaction or to acquire the lock and proceed as a non-transaction; based on the HLE predictor predicting to elide, setting the address of the lock as a read-set of the transaction, and suppressing any write by the lock- acquire instruction to the lock and proceeding in HLE transactional execution mode until an xrelease instruction is encountered wherein the xrelease instruction releases the lock or the HLE transaction encounters a transactional conflict; and based on the HLE predictor predicting not- to-elide, treating the HLE lock-acquire instruction as a non-HLE lock-acquire instruction, and proceeding in non-transactional mode.

Description

technical field [0001] The present disclosure relates generally to transactional memory systems, and more particularly to methods, computer programs, and computer systems for adaptively sharing data by utilizing lock elision and locking selection. Background technique [0002] The number of central processing unit (CPU) cores on a chip and the number of CPU cores connected to shared memory continues to grow significantly to support increasing workload capacity requirements. The ever-increasing number of CPUs cooperating to handle the same workload imposes a significant burden on software scalability; for example, shared queues or data structures protected by traditional semaphores become hot spots and lead to sub-linear n-way scaling curves. Traditionally, this has been dealt with by implementing finer-grained locking in software. Implementing finer-grained locking to improve software scalability can be very complex and error-prone, and at today's CPU frequencies, the laten...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/30087G06F9/526
Inventor M·K·克施温德M·M·迈克尔V·萨拉普拉岑中龙
Owner IBM CORP
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