Data transfer circuit

Abstract

The present invention aims to prevent data transmission errors caused by access conflicts between two devices. The solution is: in the conflict detection unit 10, when the second device is reading data from the FIFO memory 1, if the state readout signal SR1 for reading the count value of the counter 2 from the first device is detected, Then, regardless of the size of the count value of the counter 2, a value indicating that the FIFO memory 1 is full is output to the first device. In addition, in the collision detection unit 20, when the first device writes data to the FIFO memory 1, if the state read signal SR2 for reading the count value of the counter 2 from the second device is detected, regardless of the state of the counter 2 Regardless of the size of the count value, a value indicating that the FIFO memory 1 is completely empty is output to the second device.

Description

technical field [0001] The present invention relates to a data transmission circuit using a FIFO (First In First Out) buffer for data transmission. Background technique [0002] As such prior art, there is Patent Document 1, JP-A-2003-23469. [0003] figure 2 It is a structural diagram of a conventional data transmission circuit using a FIFO buffer, and it is a data communication card incorporated in, for example, data transmission between a PHS (Personal Handyphone System) and a notebook personal computer (hereinafter referred to as a personal computer) . [0004] This data transfer circuit, for example, is the one capable of transferring data from a PHS connected on the left side of the figure to a personal computer connected on the right side of the figure, and has a FIFO memory 1, a counter 2, a buffer 3 and a selector 4. [0005] The FIFO memory 1 sequentially stores write data WDT according to a write control signal WEN, and sequentially reads data from the beginnin...

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Problems solved by technology

[0008] However, the above-mentioned data transmission circuit has the following problem: when the write data WDT is written into the FIFO memory 1 from the PHS side, the count value CNT of the counter 2 read from the personal computer side will read an indeterminate count value CNT , so that the read read data RDT is more than the actual stored data

[0009] There is also the following problem: when the read data RDT is read from the FIFO memory 1 on the personal computer side, when the count value CNT of the counter 2 is read from the PHS side, an indeterminate count value CNT will be read, and the value exceeding the Write data WDT of blank area

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