Layout Design Method and Layout Design Cell Collection

Abstract

The invention provides a layout design method and a layout design unit set. The layout design unit set comprises a first unit, a second unit, a third unit, a fourth unit and a fifth unit, wherein the first unit to the fifth unit are arranged in sequence so as to form an initial layout which is used for forming an SRAM (Static Random Access Memory), and the SRAM unit comprises a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first grid transmission transistor and a second grid transmission transistor which are formed by a plurality of fin patterns, a first total grid pattern and a second total grid pattern. The layout design unit set further comprises first plug-in units. The first to the fifth units and the first plug-in units can form an SRAM unit layout. The proportion of the channel region width to length ratios of the pull-up transistors, the pull-down transistors and the grid transmission transistors in the formed SRAM unit layout can be adjusted through adjusting the number of the first plug-in units set in the SRAM unit layout, thereby being capable of designing SRAM units with various different performance conveniently, and simplifying design steps of the SRAM units.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a layout design method and a layout design unit set. Background technique [0002] Static Random Access Memory (SRAM), as a kind of volatile memory, has the advantages of high speed, low power consumption and compatibility with standard processes, and is widely used in PCs, personal communications, consumer electronics (smart cards, digital cameras, multimedia players) and other fields. [0003] In a Fin Field-Effect Transistor (Fin Field-Effect Transistor, FinFET), the gate can control the fin of the ultra-thin body from at least two sides, so the gate has a strong ability to control the channel and can be well To suppress the short channel effect. Therefore, the use of fin field effect transistors to form SRAM cells can improve the performance of SRAM cells. [0004] figure 1 A schematic diagram of an SRAM cell in the prior art is shown, which generally includes two pull-up tra...

AI Technical Summary

Problems solved by technology

In layout design, when multiple SRAM cell patterns (which may include patterns on multiple levels) in one area are the same, a designed SRAM cell pattern can be repeated in the array, but when it is necessary to design different performance In the case of SRAM cell graphics, due to the different SRAM cell graphics, it is necessary to re-design the layout of the new SRAM cell graphics, prolonging the design time, and also need to conduct process evaluation for each newly designed SRAM cell graphics to determine whether it meets the factory's process capability , presents a risk to the design

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