High-speed vertical channel three-dimensional NAND memory device

Abstract

The invention provides a memory device. The memory device is provided with a plurality of stacked conductive layers. Each vertically-oriented cylindrical body comprises memory cells connected in series. The memory cells are arranged at the intersections between the cylindrical bodies and the conductive layers. String selection lines are arranged above the conductive layers, each intersection between the cylindrical bodies and the string selection lines defines a select gate of the cylindrical bodies. Bit lines pass above the String selection lines. The cylindrical bodies are arranged on a regular grid, wherein the regular grid is rotated relative to the bit lines. The grid may have square, rectangular or rhombic memory cells, and can be rotated by an angle [theta] relative to the bit lines by the equation tan([theta])=+ / -X / Y, wherein X and Y are co-prime integers. The string selection lines can be wide enough to intersect two cylindrical bodies at one side of the memory cells or all cylindrical bodies of the memory cells, or be wide enough to intersect two or more non-adjacent cylindrical bodies of the memory cells.

Description

technical field [0001] The present invention relates to a memory device having high density, and more particularly to a memory device configured with multi-planar memory cells to provide a three-dimensional (3D) array. Background technique [0002] As the critical dimensions of devices in integrated circuits shrink to the limits of typical memory cell technology, designers have sought techniques for stacking multi-planar memory cells to achieve greater storage capacitance and lower cost per bit. For example, Lai et al. published in "A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory," IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006, and Jung et al. in "Three Dimensionally Stacked NAND Flash Memory Technology UsingStacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nmNode,"IEEE Int'l Electron Devices Meeting, 11-13Dec.2006's technical content discloses that thin film transistor technology is applied to charge trapping memory t...

AI Technical Summary

Problems solved by technology

Since the increase in memory layers also increases the number of string selection lines 12, it also results in increased power consumption and slows down device operations.

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